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Modeling >> Semiconductor Devices >> IBM45nm (SOI ) technology Gate resistance problem
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Message started by nadroit on Jul 18^th, 2011, 9:47am

Title: IBM45nm (SOI ) technology Gate resistance problem
Post by nadroit on Jul 18^th, 2011, 9:47am

I am using IBM45nm (SOI) technology provided by MOSIS for designing RF circuits. I used cadence 6.1 to carry out some simulations. When I do typical DC simulation and print the oprating points I do not see the value for gate resistance . Why is this happning? is there no gate resistance in SOI technology? (I checked the BSIMSOI manual and they do model gate resistance and ther RF parameters) I bit confused please help.

Thanks

Title: Re: IBM45nm (SOI ) technology Gate resistance problem
Post by Geoffrey_Coram on Jul 20^th, 2011, 6:36am

Did you check the documentation for BSIMSOI in your simulator and verify that RG or RGEFF or whatever is in the list of operating point values?