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Measurements >> Phase Noise and Jitter Measurements >> Divider phase noise
https://designers-guide.org/forum/YaBB.pl?num=1311262745

Message started by vin on Jul 21^st, 2011, 8:39am

Title: Divider phase noise
Post by vin on Jul 21^st, 2011, 8:39am

Hi All

I designed a digital frequency divider for my crystal oscillator(Fosc=20M) output to be divided by 2 . Basically a D flpflop in feedback configuration, when I run phase noise sims on divider alone in spectre RF i was getting -170db noise floor.

My crystal oscillator when running at 20M (i.e undivided) does have a floor of -160db. When i connected the divider i expect 6db improvement in floor for divided by 2 function which 20log(2), instead what I am getting is 10db worse than undivided noise floor. I tried different divider toplogies like DFF , master slave DFF, TSPC DFF but all of these are showing me worse noise floor than undivided output.

I do know powersupply noise do effect the divider phase noise and replaced the supply with ideal voltage source. Iam aware of broadband noise at the input of the divider get aliased so tried flitering the noise at the input of divider but the result is no improvement.

I cant understand how a 170db noise floor divider put into oscillator can degrade the phase noise? am I missing anything here?

pss setup when divider switched in is fundmental is 10MHz and selecting the output node as divider output.

can anybody have any thoughts on this?

Regards
Vin

Title: Re: Divider phase noise
Post by rfmems on Jul 21^st, 2011, 11:14pm

Was the close-to-carrier noise improved by 6dB?

Title: Re: Divider phase noise
Post by vin on Jul 22^nd, 2011, 2:19am

rfmems

Thanks for reply, yes closein is improved roughly by 6db but that is upto offsets of 100Hz.

Regards
Vin

Title: Re: Divider phase noise
Post by rfmems on Jul 25^th, 2011, 2:15am

which relative harmonic did you choose in your pnoise simulation?
When you simulte the divider alone, did you use the clock waveform as if the divider and oscillator are connected together?

Title: Re: Divider phase noise
Post by vin on Jul 25^th, 2011, 5:48am

rfmems

I used relative harmonic as 1, When I simulated the divider alone I used same rise/fall times as I would expect when oscillator and divider connected together.

vin

Title: Re: Divider phase noise
Post by rfmems on Jul 25^th, 2011, 7:26am

Hi vin,

How about the load effect of the divider on your osc when you simulate the osc noise alone?

Normally you don't see 6dB noise improvement at 20MHz offset for the following reasons, (1) the 20MHz noise are dominant by buffer and divider noises instead of osc noise itself. (2) at 20MHz offset, AM noise contributes as well to your noise floor.

What I am trying to find out is why it is 20dB worse than your divdier simulation.

regards
RFMEMS