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Design >> RF Design >> PLL loop filter connection to vco and test
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Message started by .matteo on Sep 1^st, 2011, 2:58am

Title: PLL loop filter connection to vco and test
Post by .matteo on Sep 1^st, 2011, 2:58am

Hi everybody,
I am designing a integer-N PLL and I would like to have some suggestions about two things:

1. what is the best way to connect the tuning voltage to the pad? are you using a multiplexer, a switch or something different?

2. I'm experiencing some problems when I connect the loop filter to the VCO varactor (differential gate-connected MOS diodes). I guess it's due to the varactor leakage. What is the best way to connect the varactor to the VCO and the tuning voltage?

Thanks
Matteo

Title: Re: PLL loop filter connection to vco and test
Post by raja.cedt on Sep 1^st, 2011, 3:26am

hello,
1. How to connect Vcontrol node to pad.
If you use use transmission gate or multiplexer you would face much voltage drop (at least in lower cmos technology), so i have used unity gain opamp whenever i want to switch off simply i power down opamp.

2. I didn't understand wht problem you are facing, please write clearly.

Thanks.

Title: Re: PLL loop filter connection to vco and test
Post by rfcooltools.com on Sep 1^st, 2011, 1:50pm

matteo,

In absence of information exactly describing your issue. Here are some thoughts on what to check.

you are using a mos varactor where the source/drain is tied to your VCO core and the gate is tied to the vtune voltage.
Does the device sit inside a well?
What voltage is the well tied to?
If the well is modeled and has a pin is current entering/leaving this pin if so what is the magnitude?
Is the signal swing large enough to turn on a parasitic diode?
If this is occurring is this related to the varactor Q at some voltages?
you are experiencing problems when the loop filter is tied to the varactor describe what you are experiencing.
How balanced is your VCO tank?
Is there a fair amount of common mode voltage on the loop filter?
If so why?

Varactors shouldn't leak to a level where the performance is poor or they wouldn't be good for most of the foundries customers.

In addition:
Check to make sure your varactor is connected correctly, a lot of times checking the model and confirming the physical structure is modeled correctly is essential. At least a couple times in my carrier I have witnessed a colleagues VCO's being built where a parasitic diode was not in the model, but was there in the real application.

http://rfcooltools.com

Title: Re: PLL loop filter connection to vco and test
Post by .matteo on Sep 2^nd, 2011, 1:10am

@raja.cedt
thanks for the reply, unity gain opamp may be a good solution except for the fact that a rail-to-rail operation would complicate a bit its design. I will try to clarify the problem a little bit more.

@rfcooltools.com
Thank you very much for the reply.
I'm using a mos varactor where the source/drain is tied to the VCO core and the gate to the control voltage. It sits in a nwell that is floating. I have access to the substrate through a pin but that pin only biases an external guard ring (pwell substrate) and not the nwell.

I run a PSS simulation where I produce a rail to rail differential swing at the drain/sources of the varactor and connect the tuning voltage to a loop filter biased to 600mV. It produces a second harmonic ripple of 3mV, is that normal? I think that such a ripple should not impair the VCO functions but I'm worried anyway.

To clarify my problem:
So far I simulated the PLL with a veriloga model of the VCO because I thought that no problems / differences may arise from connecting the real VCO to the loop filter. However, once I connect it, I see a small ripple in the control voltage (twice the output freq) plus my control voltage looks like a sawtooth wave (reference period), that is not good at all. Is there something I may be doing wrong? That's the reason why I was wondering what is the best way to connect the varactor to the tuning voltage.

Any suggestion is really appreciated
Thanks

Title: Re: PLL loop filter connection to vco and test
Post by .matteo on Sep 2^nd, 2011, 2:10am

I realized that the sawtooth is caused by a current at 2*fvco generated by the varactor. This current varies with the tuning voltage (I think because the varactor is biased differently and generates different second harmonic distortion). So my question is: should I use the varactor bias configuration of my second picture? What is the impact of that two big resistors on VCO phase noise? Is there a better way to do it?

Thanks

Title: Re: PLL loop filter connection to vco and test
Post by loose-electron on Sep 6^th, 2011, 4:31pm

one major thing you are not looking at - Bringing the VCO controil voltage outside the chip is going to increase jitter in a very big and very ugly manner.

Consider keeping the control node inside the chip and the filter inside the chip.

If you reall have to see this signal outside the chip, either buffer it (op-amp unity gain sort of setup) or include a well isolated switch string (mult series switch with middle nodes grounded out when turned off) which removes coupling to the outside world when it is off.

Flipping that on/off will show significant changes in the jitter.

Title: Re: PLL loop filter connection to vco and test
Post by .matteo on Sep 7^th, 2011, 3:13am

loose-electron wrote on Sep 6^th, 2011, 4:31pm:

Thanks for your answer.

I will definitely not take the control voltage outside the chip. I did further simulations about phase noise and I convinced myself that both the solutions I proposed to bias the varactor are horrible in terms of phase noise performance. I'm designing a higher order PLL to remove the 2*fvco current spurs coming from the varactor.

Thanks for the suggestion about the buffer. I think I will design a series of two transmission gates and ground the middle node when not using them ..so if the PLL does not work I can still force the tune voltage from outside.

I have a question: do you have other suggestions about how to layout the PLL to minimize the coupling and the noise from the substrate?

Thanks,
Matteo

Title: Re: PLL loop filter connection to vco and test
Post by raja.cedt on Sep 7^th, 2011, 4:31am

hello,
is your design is integer-N ot factional? How much your ref-spur spec? If you are doing interger-N then i don't think 2*fvco ripple on the control will be problem because they will be far from loopBW..

Thanks.

Title: Re: PLL loop filter connection to vco and test
Post by .matteo on Sep 7^th, 2011, 4:43am

raja.cedt wrote on Sep 7^th, 2011, 4:31am:

My design is integer-N.
Unfortunately, the 2*fvco current flowing inside the loop filter from the varactor does not have zero average and its average depends on the voltage tuning-voltage-vco-output. So it actually charges the filter and it is a problem.

Title: Re: PLL loop filter connection to vco and test
Post by rfcooltools.com on Sep 7^th, 2011, 2:53pm

Matteo,
Responding to your question:
"So my question is: should I use the varactor bias configuration of my second picture? What is the impact of that two big resistors on VCO phase noise? Is there a better way to do it?"

Taking a step back if you get second harmonic on the varactor try to find the source. You can do this by monitoring the voltages and currents entering and leaving the varactor nodes.
If your VCO swing is so large that it activates a parasitic diode in the varactor, or the varactor capacitance change over a period is causing the VCO to swing somewhat wonky. Consider lowering the voltage swing on the varactor by making the caps in series with it smaller. The loss of tuning range can be made up by switching in/out caps. This approach is common plus usually it provides the best phase noise overall.

http://rfcooltools.com

Title: Re: PLL loop filter connection to vco and test
Post by .matteo on Sep 8^th, 2011, 12:51am

rfcooltools.com wrote on Sep 7^th, 2011, 2:53pm:

@rfcooltools.com
Thanks for the suggestion but I don't think it's a good idea (I mean, lowering the VCO swing by making the caps in series with the varactor smaller). If you decrease the caps to get less second harmonic current, you really need a huge varactor (or a bank of varactor) to get the same varactor tuning range. Do you agree?

Title: Re: PLL loop filter connection to vco and test
Post by rfcooltools.com on Sep 8^th, 2011, 9:39am

Matteo,

Actually I am saying something different by when I inferred lowering the vco swing across the varactor. My intention is not just making the series caps smaller, but in addition to this switching in a fixed cap based on desired output frequency. My intention is not to increase the varactor size compensate for the tuning range.

Here is an analogy:
think of a varactor as an automobile engine throttle. If you want to go from 0 to 20 (mph/kph) then you wont need to shift gears. if this is all your automobile only needs to go within this range then there really is no need for a transmission. but if your automobile needs to cover a wide range of speeds then either you need an engine that can handle a huge range of rpm's for a single gear or (a more practicable way) you can use multiple gears and reduce the rpm requirements on the engine.

You are trying to build an automobile that only has one gear! instead have your vco switch gears by switching in a fixed amount of capacitance for a range of frequency. Then the varactor does not need to cover such a large range.

http://rfcooltools.com

Title: Re: PLL loop filter connection to vco and test
Post by .matteo on Sep 10^th, 2011, 12:57am

@rfcooltools.com
Thanks for clarifying. Sorry if I wasn't clear enough but I already have a capacitor bank to "switch gear" ::) ..it's just that it's not part of the pictures above because it was not part of my question.

Title: Re: PLL loop filter connection to vco and test
Post by rfcooltools.com on Sep 10^th, 2011, 11:31am

Matteo,
Sorry for the confusion, but if you already have the switchable cap then could you not just add another LSB cap and then reweight the varators contribution to tuning?

http://rfcooltools.com

Title: Re: PLL loop filter connection to vco and test
Post by loose-electron on Sep 12^th, 2011, 9:57am

.matteo wrote on Sep 7^th, 2011, 3:13am:

I have a question: do you have other suggestions about how to layout the PLL to minimize the coupling and the noise from the substrate?

Thanks,
Matteo

It is not a simple one line answer. Extensive grounding substrate contacts enclosing the structure, and within the structure and its controlling driver (the filter) to establish a common low impedance reference ground. Keep the system differential, and balanced in structure.

Best I can do in a short summary.