The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Analog Verification >> Analog Functional Verification >> Linter for VHDL-AMS, Verilog-AMS https://designers-guide.org/forum/YaBB.pl?num=1315218155 Message started by hakke on Sep 5th, 2011, 3:22am

Title: Linter for VHDL-AMS, Verilog-AMS Post by hakke on Sep 5th, 2011, 3:22am Hi! Is there a linting tool for analog design blocks? We have mixed signal designs where the top level is analog. For RTL we use SpyGlass to do static code analysis. But due to presynthesis, this tool does'nt work with behavioral code. So, is there a similiar tool for analog designs? BR, hakke

The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved.