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Modeling >> Behavioral Models >> clock and data recovery (CDR)  modeling using simulink
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Message started by tky86 on Sep 29th, 2011, 5:47pm

Title: clock and data recovery (CDR)  modeling using simulink
Post by tky86 on Sep 29th, 2011, 5:47pm

Hi, anyone has been modeling CDR by using simulink? CDR archictecture i am doing right now is dual-loop PLL-based CDR. I faced some problems that i don't know how to model the lock detector in simulink? could anyone tell me what is the block inside the lock detector?

Thanks.

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by loose-electron on Oct 27th, 2011, 5:12pm

there are several different ways of modelling a PLL in simulink - can you post a drawing of what you got?

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by Johan Japp on Nov 1st, 2011, 4:12am

No on can tell exactly uptill you couldn't post any drawing but still I am providing you one link go there may you will get some thing in it:

ieeexplore.ieee.org/Xplore/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F4443903%2F4443904%2F04443922.pdf%3Farnumber%3D4443922&authDecision=-203

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by tky86 on Nov 2nd, 2011, 7:54pm

I have attached the reference design. I'm wondering if lock detector i want to include into the dual-loop CDR, what is the compenent inside the block of the lock detector in simulink?

The concept of the lock detector is that at start up, the coarse loop will provide fast locking to the system frequency with the help of reference clock, after the VCO reach proximity of the system frequency, lock detector toggles the "lock" signal indicating that it is time for the fine loop to take over the control of phase locking.

Have anyone have ideas about how to model the lock detector together with the phase/frequency detector (PFD) together in matlab??

Thanks and appreciate alot. :)

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by loose-electron on Nov 5th, 2011, 1:21pm

OK, the block you are describing can be done as a boolean function to create the equivalent of a phase-frequency detector.

Than can be done from the logic library with Nand gates, S-R latches and delay elements. Google the structure for a phase-frequency detector.

Lock detection? How about a design where the VCO control voltage has gone flat for a period of time.

I see you are in Malaysia - I taught at the UTP outside KL a few years back. Nice campus facility.

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by tky86 on Nov 10th, 2011, 5:46pm

HI loose-electron,

Yes, I come from Malaysia. Thanks for your reply. I manage to simulate the phase-frequency detector (PFD) alone to get the desired output.

However, i still not get it how you describe the lock detector in simulink? How i should design in simulink in order to differentiate the fine loop and coarse loop?

Thanks and aprreciate alot. :)

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by loose-electron on Nov 12th, 2011, 4:34am

Lock detector - several possible methods -

Look at the digital output of the PFD (phase  freq detector)
and determine when the device has stopped actively pumping. Add a digital delay and the result is detection of lock.

Look at the output of the PLL filter, take the derivative of the voltage and determine when the derivative is near zero.

Both should work, the digital method is probably smaller in size and less power consumed.

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by tky86 on Nov 14th, 2011, 1:45am

Hi loose-electron,

Do you have any simulink diagram regarding what you have suggesting your work?

thanks alot.
:)

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by tky86 on Dec 6th, 2011, 7:08pm

Hi Everyone,

Could anyone tell me how to simulate the eye diagram in simulink?

Could list down step by step how to setup the eye diagram or any diagram to refer to?

Thank alot and appreciate it.

Title: Re: clock and data recovery (CDR)  modeling using simulink
Post by pcardoso73 on Jul 3rd, 2013, 11:23am

Hi all,

I am sorry to post here 2 years afterwards, but I have a similar problem, and I didn't want to create a new thread on the same subject.

I am doing a macro-model of a PLL in Simulink and  I cannot put the PFD to work. I am using the usual block diagram: 2 DFF's, 1 AND gate, input and output ports. However this is not that easy. I have googled and I have found nothing. Can anybody help me ? I am stuck !!!

The goal of this is to have a functional PLL, and then add noise to each one of the blocks.

Cheers,
Pedro

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