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Design Languages >> VHDL-AMS >> newbie question on VHDL-AMS
https://designers-guide.org/forum/YaBB.pl?num=1318655712

Message started by ethanlinear on Oct 14^th, 2011, 10:15pm

Title: newbie question on VHDL-AMS
Post by ethanlinear on Oct 14^th, 2011, 10:15pm

architecture bhv of fc_jtol_src_ns is
constant rt, ft : real := 20.0e-12;
terminal clk_in : electrical;
signal cjtpat : std_logic := '0';
signal cjtpat_real : real := 0.0;
quantity cjtpat_quant : voltage;
quantity vdata_out across idata_out through data_outp to data_outn;
begin

i_clk_gen : entity LIB_AMS.clk_gen(str)
port map (
sj_freq => sj_freq,
sj_amp => sj_amp,
udj_amp => udj_amp,
freq => freq,
nreset => nreset,
sin_clk => clk_in);

i_rj_src : entity LIB_AMS.rj_src(bhv)
port map (
rj_amp => rj_amp,
rj_out => clk_in);

i_cjtpat_gen : entity LIB_AMS.cjtpat_gen(bhv_str)
port map (
nreset => nreset,
clk_in => clk_in,
cjtpat => cjtpat);

cjtpat_d2a: process (cjtpat)
begin
if cjtpat = '0' then
cjtpat_real <= data_vcm - data_amp / 2.0;
else
cjtpat_real <= data_vcm + data_amp / 2.0;
end if;
end process cjtpat_d2a;
cjtpat_quant == cjtpat_real'ramp(rt, ft);
vdata_out'dot / (MATH_2_PI * ddj_fc) + vdata_out == cjtpat_quant;
end bhv;

What does it mean with "vdata_out'dot / (MATH_2_PI * ddj_fc) + vdata_out == cjtpat_quant;"? Is this a low pass filter? Thanks,