The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Measurements >> Phase Noise and Jitter Measurements >> dependency of Charge Pump induced jitter on pulse width
https://designers-guide.org/forum/YaBB.pl?num=1320756083

Message started by rajkumar palwai on Nov 8^th, 2011, 4:41am

Title: dependency of Charge Pump induced jitter on pulse width
Post by rajkumar palwai on Nov 8^th, 2011, 4:41am

Hi all,

In a PLL, typically we keep finite pulse widths for UP & DOWN signals to avoid the dead band. How does this pulse width affect my charge pump noise contribution to the entire pll jitter (keeping the ref clk freq constant)?

Typically in any sampled systems, we never bother about the duty cycle of the sampling clock. We always say that the integrated power withing fs/2 is 'KT/C'. If that is the case then i think the charge pump induced noise (or jitter) is also independent of the UP & DOWN pulse widths and does not change.

Can some one explain if i am correct?

thanks
rajkumar

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by raja.cedt on Nov 8^th, 2011, 7:40am

hello rajkumar,
I guess jitter will increase with pulse width, because more time both and dn will be on so more charge pump noise. However your example of KT/C has no proper correlation here, becaz there Power Spectrul density increases with R and integration BW decreases with R, so you there will be no effect of on the total area, where as in case of pll Charge pump noise pSD depedns on the chargepump current and many other parameters but integration BW depends on PLL bw.

correct me if i am worng
Thanks,
Raj.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by rajkumar palwai on Nov 8^th, 2011, 9:01am

Raja,
Let u keep the PLL loop BW aside for some time. If we do the noise analysis on only charge pump(setup includes just PFD+CP+LPF. There is no VCO and PLL loop). Then the integrated noise on the LPF cap would be KT/C. right? And this integrated noise does not change with the min pulse width.

And now whatever noise PSD on the LPF cap is again band limited by the PLL loop UGB. Hence i thought the total jitter is independent of the pulse widths. Correct me if any of my assumptions are wrong.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by raja.cedt on Nov 8^th, 2011, 9:46am

hello rajkumar,
Okay forget about pll BW.

1.Are you agree on "total PSD of the chargepump increase with turn on time"
2. How you get KT/C..have you derived? I am tring to derive i got very big expression? Please find the attched integral (let me know if any thing wrong in that)

But intutively i can say 99% it won't be Kt/c because PSD depends on gm of the charge pump and BW is depends on some thing else which is depends on completly loopfilter

Thanks,
raj.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by rajkumar palwai on Nov 8^th, 2011, 9:18pm

Hi Raja,
Thanks for your time.

To say frankly, i have not derived any expression. I agree that the integrated noise is not KT/C, because noise depends on gm and BW depends on something else.

But my only point is that how is the integrated noise depending on duty cycle of up & down pulses.

If u just take a simple example: a ideal nmos is connected in series with the capacitor. And the nmos is switched on and off with a clock. Now, what would be the integrated noise voltage on the cap? Does it depend on clk duty cycle?Is this case any different from the chg pump case.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by raja.cedt on Nov 9^th, 2011, 1:11am

hello rajkumar,
PSD depends on duty cycle, because you are not pumping noise current entire reference cycle.

Please check equation4 from the following pap

http://iroi.seu.edu.cn/jssc9899/33ssc98/33ssc12/pdf/33ssc12-craninckx.pdf

If you consider simple sample hold ckt, there total integrated noise is KT/C i agree, but have u derived this any time? it's not a simple integral, because when the switch tuns on resister (mosfet) noise will be stored on the cap This component PSD is 4KTR*(duty cycle), but during holding you aliasing components so if you add these two components we are getting KT/C.

Thanks,
raj.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by rajkumar palwai on Nov 9^th, 2011, 3:48am

Thanks raja,

I have seen the KT/C derivation of the sample & Hold ckt in one of the ken kunderts paper. But i have another doubt. Even in the charge pump, we are sampling the noise when the current sources are ON and then holding that noise voltage. So you should get the aliasing here also and hence the total noise is KT/C again.

Pardon my ignorance, but am still feeling that both the charge pump and sample&hold ckts are similar and both should give same noise.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by raja.cedt on Nov 9^th, 2011, 4:44am

hello rajkumar,
let me know if get any ans, now a days i am not working on PLL's, so i hope some PLL expert can explain better. But one thing is it's not KT/C.

Thanks,
raj.

Title: Re: dependency of Charge Pump induced jitter on pulse width
Post by raja.cedt on Dec 5^th, 2011, 1:28pm

hello rajkumar,
you will get ans for your Question here

Folding of Phase Noise Spectra in Charge-Pump
Phase-Locked Loops Induced by Frequency Division

Thanks,
Raj.