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Measurements >> Phase Noise and Jitter Measurements >> Jitter estimation on synchronous counter
https://designers-guide.org/forum/YaBB.pl?num=1320886468

Message started by thechopper on Nov 9^th, 2011, 4:54pm

Title: Jitter estimation on synchronous counter
Post by thechopper on Nov 9^th, 2011, 4:54pm

Dear colleagues,

Assuming I know how much jitter my reference clock has, I need to estimate de jitter of synchronous counter of N stages.
If the reference clock jitter is jck my gut feeling is that the total jitter should be jck*√N (assuming uncorrelated jitter between stages).

Is this correct? Any other considerations (or references)?

Thanks
Tosei

Title: Re: Jitter estimation on synchronous counter
Post by rajkumar palwai on Nov 9^th, 2011, 8:28pm

Tosei,
For any flip-flop, the inherent noise in the devices also add jitter at the o/p. So, if the ref clk has jitter of 'jck' and the device noise add a jitter of 'jdn', then the total jitter at the o/p would be rms average of jck & jdn.

For synchronous dividers, jitter doesn' accumulate between stages. Because the jitter at the o/p of the final flop just depends on the jck and its own noise at that time.

Title: Re: Jitter estimation on synchronous counter
Post by rajkumar palwai on Nov 9^th, 2011, 8:29pm

Jitter accumulation happens in ripple counters where, each stage jitter affects the next stage transition.