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https://designers-guide.org/forum/YaBB.pl Design Languages >> VHDL-AMS >> counter https://designers-guide.org/forum/YaBB.pl?num=1320976172 Message started by techkid_15 on Nov 10th, 2011, 5:49pm |
Title: counter Post by techkid_15 on Nov 10th, 2011, 5:49pm I am trying to make a counter that goes from 0 - 999 on the rising edge of the clock. I am using the Nexys 2 FPGA board, so I have a 50 MHz clock, and I am using the 23rd division, or 2.98 Hz. I have 4 modules and a top level file. Top Level File: module binbcd10_top(input wire mclk, output wire [6:0] a_to_g, output wire [3:0]an, input wire [3:3]btn ); wire [9:0]w; wire [11:0] pp; binbcd10 U1 (.b(w), .p(pp)); mux7seg U2 (.a(pp[3:0]), .b(pp[7:4]), .c(pp[11:8]), .d(4'b0000), .mclk(mclk), .a_to_g(a_to_g), .an(an) ); counter U3 (.p(clk), .clr(btn[3]), .w(w)); counter_clk_div U4 (.clr(btn[3]), .mclk(mclk), .clk(clk)); endmodule Binary to Decimal Convertor: module binbcd10(input wire b, output reg [11:0]p ); reg[21:0]z; integer i; always @ (*) begin for (i=0; i <= 21; i=i+1) z[i]=0; z[14:3] = b; for (i=0; i<5; i=i+1) begin if(z[13:10] > 4) z[13:10] = z[13:10] + 3; if(z[17:14] > 4) z[17:14] = z[17:14] + 3; if(z[21:18] > 4) z[21:18] = z[21:18] + 3; z[21:1] = z[20:0]; end p = z[21:10]; end endmodule This tells it how to display numbers on the 7 segment displays: module mux7seg(input wire mclk, output reg [6:0]a_to_g, output reg [3:0]an, input wire [3:0] a, input wire [3:0] b, input wire [3:0] c, input wire [3:0] d ); wire [1:0] s; reg [3:0] y; reg [19:9] clkdiv; assign s[1] = clkdiv[19]; assign s[0] = clkdiv[18]; always @ (*) case(s) 0: y = a; 1: y = b; 2: y = c; 3: y = d; default: y = a; endcase always @ (*) case(y) 0:a_to_g =7'b0000001; 1:a_to_g =7'b1001111; 2:a_to_g =7'b0010010; 3:a_to_g =7'b0000110; 4:a_to_g =7'b1001100; 5:a_to_g =7'b0100100; 6:a_to_g =7'b0100000; 7:a_to_g =7'b0001111; 8:a_to_g =7'b0000000; 9:a_to_g =7'b0000100; 'hA:a_to_g =7'b0001000; 'hB:a_to_g =7'b1100000; 'hC:a_to_g =7'b0110001; 'hD:a_to_g =7'b1000010; 'hE:a_to_g =7'b0110000; 'hF:a_to_g =7'b0111000; default a_to_g=7'b0000001; endcase always @ (*) begin an = 4'b1111; an[s] = 0; end always @ (posedge mclk) clkdiv <= clkdiv +1; endmodule Counter: module counter(input wire p, output reg [15:0]w, input wire clr ); always @ (posedge p or posedge clr) begin if(clr == 1) w <= 0; else if(w == 999) w <= 0; else w <= w +1; end endmodule Clock Divider: module counter_clk_div(input wire clr, input wire mclk, output wire clk ); reg[23:0] q; assign clk = q[23]; always @ (posedge mclk or posedge clr) begin if(clr == 1) q <=0; else q <= q +1; end endmodule Right now, it is just alternating between a 0 and 1 on the far right 7 segment display. I appreciate any help. |
Title: Re: counter Post by boe on Nov 11th, 2011, 8:14am techkid_15, Bug in interface of binbcd10 (port b) block. - B O E |
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