The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Measurements >> Phase Noise and Jitter Measurements >> PLL based on current starved VCO simulation/design issues
https://designers-guide.org/forum/YaBB.pl?num=1321046952

Message started by lunren on Nov 11^th, 2011, 1:29pm

Title: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 11^th, 2011, 1:29pm

Hi All,

I am working on a PLL design now. The VCO is a pseudo differential one with four delay stages (two inverter rings with cross coupled inverters) to generate quandrature outputs. I choice this structure for VCO because of the limited current consumption spec. Now there are two problems:
1) In the design of VCO, I always kick off VCO to start to oscillate; however in PLL simulation (no kick off), I found four stage VCO is harder to start to oscillate compared to three stage VCO (I changed the VCO to three stages just to see if it is oscillating). But principally, four stage VCO should be easier to oscillate than three stage. Does any one have this problem before? For the four stage VCO, when I added more decoupling cap, then it becomes harder to oscillate and sometimes it seems doesn't start to oscillate (maybe simulation time is not long enough?) Should I worry about the start up problem in real silicon? If it doesn't start to oscillate in simulation, can I add kick off in PLL simulation?
2) The ripple on the control voltage is around 20mV (the same frequency as VCO frequency) which is about 3% variation. However, since it is a current starved VCO, I measured the current variation, which is only 0.17%. Should I worry about the ripple on the control voltage? In self biased VCO design, my design experience is the ripple is less than 100uV. But in current starved VCO, 20mV just make me worry about it.

Any comments are welcome.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by loose-electron on Nov 11^th, 2011, 1:58pm

Depends on the polarity of how you feed things back.

Be careful you don't create a latch.

Also for the delay stages look into the Maneatis PLL delay structure. Works well, and is fully differential.

www.truecircuits.com/images/pdfs/maneatis96b.pdf

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 11^th, 2011, 4:55pm

Attached is the schematic of my VCO, it is a four stage VCO. The delay inverter is 4 time stronger than the regenerative inverter. Should not become a latch.

We want to save power and reduce the complexity of the circuit, so this is why I didn't choice Maneatis VCO.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 11^th, 2011, 6:19pm

lunren wrote on Nov 11^th, 2011, 1:29pm:

Hi All,

2) The ripple on the control voltage is around 20mV (the same frequency as VCO frequency) which is about 3% variation. However, since it is a current starved VCO, I measured the current variation, which is only 0.17%. Should I worry about the ripple on the control voltage? In self biased VCO design, my design experience is the ripple is less than 100uV. But in current starved VCO, 20mV just make me worry about it.

Any comments are welcome.

The ripple of 20mV might not be true. Since I have power and ground routing resistor and the control voltage is referenced to ground. If I take the difference between control voltage and ground, then the ripple by VCO itself becomes very very small. Only charge pump mismatch induced ripple is a concern now.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by raja.cedt on Nov 12^th, 2011, 2:52am

hello runren,
1.When you simulate VCO, you have to apply some stimulus to start oscilations because it is an autonomous circuit, where as in pll no need to apply stimulus to kick oscilations becaz it's a driven ckt. If pll is failing to oscilate then problem might be with VCO.

2.regarding your word ' four stage VCO should be easier to oscillate than three stage'. Have estimated Q of the oscilator? upto my knoeledge it's tough to generalize and more over what do you mean by HARDER TO OSCILATE. I suggest you to do AC analysis and estimate Q.

3. Maneatis is not so power hungry, infact it is very suitable in noise supply PLL becaz of it's self bias.

4. I am assuming that you have control voltage @ the loop filter and with this you are generating controling current by V to I converter (may be single transister many times), if this is correct then ripple on the control voltage matters (after all control voltage and control current is related by V to I conveter). One more Question is your frequency of ripple on the control voltage is not same as your VCO frequency (i guess it is four times)

Sorry for the big reply.

Thanks,
Raj.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by raja.cedt on Nov 12^th, 2011, 4:00am

hello
i forgot to ask you, whats the delay cell architectures?

Thanks,
raj.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 13^th, 2011, 12:44am

Quote:

1.When you simulate VCO, you have to apply some stimulus to start oscilations because it is an autonomous circuit, where as in pll no need to apply stimulus to kick oscilations becaz it's a driven ckt. If pll is failing to oscilate then problem might be with VCO.

Yes, I guess you are right.

Quote:

2.regarding your word ' four stage VCO should be easier to oscillate than three stage'. Have estimated Q of the oscilator? upto my knoeledge it's tough to generalize and more over what do you mean by HARDER TO OSCILATE. I suggest you to do AC analysis and estimate Q.

I didn't estimate Q of the oscillator yet. You mean it might not always correct to say "more stage means easier oscillation"? In typical corner, both PLLs (three stage VCO and four stage VCO) can oscillate, PLL with three stage VCO starts to oscillate earlier though; in slow corner, PLL with four stage VCO doesn't oscillate while PLL with three stage VCO oscillates. Since the VCO is inverter based ring, how can I run AC to get Q?

Quote:

3. Maneatis is not so power hungry, infact it is very suitable in noise supply PLL becaz of it's self bias.

I designed Maneatis PLL before, compared to this inverter based current starved pseudo differential VCO, Maneatis VCO still consumes more current (more parasitic caps because of the complexity and self bias circuit consume current).

Quote:

4. I am assuming that you have control voltage @ the loop filter and with this you are generating controling current by V to I converter (may be single transister many times), if this is correct then ripple on the control voltage matters (after all control voltage and control current is related by V to I conveter). One more Question is your frequency of ripple on the control voltage is not same as your VCO frequency (i guess it is four times)

Yes, I have V2I converter following loop filter. There are absolute ripple on the control voltage, however, if I refer control voltage to local ground of V2I circuit, the ripple is ignorable. In my simulation, I put a routing resistor in the ground power so there are ripples. Yes, the ripple frequency is four times that of VCO frequency.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 13^th, 2011, 12:52am

raja.cedt wrote on Nov 12^th, 2011, 4:00am:

hello
i forgot to ask you, whats the delay cell architectures?

Attached please find the delay cell architecture. The delay inverter is four times stronger than the regenerative inverter. Another advantage of this structure is that the duty cycle is very good.

Chip supply voltage is 1.8V, I have on chip LDO which generate 1.5V for VCO. but the real supply voltage to the delay cell is about 0.9V because of the V2I converter.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by raja.cedt on Nov 13^th, 2011, 2:23am

hello,

1.You can find any oscilator Quality factor by using .pz, just add a ac current source for input, then spectre display pole zero locations with Quality factor and that you can find a a RHP with imganary value very near to frequecy of oscilations (due non-linearity). You can see the attched fig.

2. Razavi has coined a new Q factor, in this tthe following pap, there he calculated Q for 3 stage oscilator. http://www1.ee.ucla.edu/~brweb/papers/Journals/BRMar96.pdf

3. In slow corner you are saying 4 stage oscilator is not working means design is not good

4. I agree with you regarding mennaties cell but one good thing it doesn't need regulator up to some extent.

Thanks,
raj.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 13^th, 2011, 1:07pm

Hi raj.

I think I found the problem of the design. If it is a odd stage VCO with the cross coupled inverter delay stage, then PLL will oscillate when delay inverter is 3~4 times stronger than regenerative inverter. However, it is is an even stage VCO (here it is four), then "3~4 times" doesn't work. The regenerative inverter should be a little bit stronger. In my case, "2 times" works well in all corners.

Since it is a inverter (one PMOS + one NMOS) chain, it seems hard to use ac to simulate quality factor or loop gain. Maybe I need bias the circuit at middle rail.

Thanks,

Lunren

Title: Re: PLL based on current starved VCO simulation/design issues
Post by raja.cedt on Nov 14^th, 2011, 12:23pm

hello lunrun,
yes you can just bias the ring oscillator by inverter with feedback. In fact the results what i shown is for 3 stage ring oscillator.

Thanks,
Raj.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 14^th, 2011, 9:27pm

Hi raj,

Another question is that do we have a general criteria for Q factor? How good is good? I understand that as long as there is a RHP pole, the oscillator should work, but in terms of Q factor, I am not sure the margin criteria.

Thanks,

Lunren

Title: Re: PLL based on current starved VCO simulation/design issues
Post by raja.cedt on Nov 15^th, 2011, 1:17am

hello,
yes you are correct, as long as you have gain>1 and pole in right half oscilator will start oscilating in growing fashion, and if it has growing non-linerity it will be settled for constant amplitude. But Q is some thing else which impacts 1. How fast it settles 2. How better the rejection of noise (a.k.a Phase noise). The more Q you have the better Phase noise. So use phase noise and Q relation. But this is more common for LC but you can do for ring as well.

Thanks,
Raj.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by loose-electron on Nov 15^th, 2011, 5:43pm

Q in a ring oscillator is pretty meaningless IMHO

This structure is not differential it is complementary. There is a big difference.

Expect this structure to have lots of jitter problems due to noise sensitivity to both power and ground.

Title: Re: PLL based on current starved VCO simulation/design issues
Post by lunren on Nov 15^th, 2011, 6:47pm

People called it pseudo differential. It still has some power and ground rejection, but not that much as fully differential. I read paper people used it to generate ring oscillator with a PN over -100dBc/1Mhz. I found a lot of people currently are using this structure (from ISSCC 2011 digest of technical papers book).

Title: Re: PLL based on current starved VCO simulation/design issues
Post by loose-electron on Nov 21^st, 2011, 2:29pm

In a noise environment, I would expect it to have problems...