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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Req example of pulldown command in VerilogA https://designers-guide.org/forum/YaBB.pl?num=1322849062 Message started by animotion on Dec 2nd, 2011, 10:04am |
Title: Req example of pulldown command in VerilogA Post by animotion on Dec 2nd, 2011, 10:04am Forum Users, I need to model a pulldown function in VerilogA. When the cntrl signal is high, this closes a mosfet switch and the signal of interest is then pulled to ground. This is the circuitry that I must model. I am aware that there is a pulldown function in VerilogA (correct me if I am wrong). However, I do not know how to use the function. Can someone please provide an example here that shows how to use it? animotion |
Title: Re: Req example of pulldown command in VerilogA Post by Geoffrey_Coram on Dec 5th, 2011, 1:21pm pulldowns are mentioned in the Verilog-AMS LRM, but I don't think of them as being part of Verilog-A. The syntax is: pulldown [pulldown_strength] pull_gate_instance { , pull_gate_instance }; pull_gate_instance ::= [ name_of_gate_instance ] ( output_terminal ) pulldown_strength ::= ( strength0 , strength1 ) | ( strength1 , strength0 ) | ( strength0 ) So: pulldown pd1 (out); would instantiate a pulldown named "pd1" on the node "out" |
Title: Re: Req example of pulldown command in VerilogA Post by boe on Dec 6th, 2011, 4:52am Geoffrey, the pulldown of Verilog-AMS is digital, so it won't work in Verilog-A. I suggest a resistor to GND. - B O E |
Title: Re: Req example of pulldown command in VerilogA Post by animotion on Dec 6th, 2011, 8:34am BOE Thank you for the reply. How do I write the resistor to ground to model the circuitry that I describe? animotion |
Title: Re: Req example of pulldown command in VerilogA Post by animotion on Dec 6th, 2011, 8:47am Geoffrey & BOE The VerilogA LRM lists pulldown as a VerilogA HDL keyword in the Appendix but it does not give an example of is use. The code that Geoffery gives may apply to VerilogA too. I will try this with the cntrl on the mosfet tested in an if statement. Paul |
Title: Re: Req example of pulldown command in VerilogA Post by animotion on Dec 6th, 2011, 10:37am The pulldown as described is not working for me in VerilogA. I am willing to try out the resistor to ground if either of you could show me the code. |
Title: Re: Req example of pulldown command in VerilogA Post by boe on Dec 6th, 2011, 10:57am You could try something like: Code:
- B O E |
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