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Modeling >> Behavioral Models >> how to create an n-stage RC filter in Verilog-A
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Message started by sorgin1 on Feb 1^st, 2012, 11:10am

Title: how to create an n-stage RC filter in Verilog-A
Post by sorgin1 on Feb 1^st, 2012, 11:10am

Hi,

The following code for a 2-stage RC filter in the following code works ok.

Code:

The next step would be use a for loop to create as many stages as I want. I tried using the following code, but fails at compile.

Code:

`include "discipline.h"

module rc_ladder_forloop(c[0],c[2], gnd) ;
inout c[0],c[2], gnd;
electrical [0:2] c;
electrical gnd;

parameter r=1k ;
parameter c=1n ;

genvar k;

analog begin
for (k=1; k<2;k=k+1) begin
I(c[k],c[k+1]) <+ V(c[k],c[k+1]) / r;
I(c[k+1],gnd) <+ ddt( V(c[k+1],gnd) * c );
end
end
endmodule

Any suggestions on how to fix this?

The next step would be to pass the number of stages as a parameter. Would that be possible? and how?

Thanks in advance.

Regards, sorgin

Title: Re: how to create an n-stage RC filter in Verilog-A
Post by boe on Feb 2^nd, 2012, 3:30am

Sorgin1,
try the generate statement or a genvar declaration.
You may want to check in your tool vendor's documentation to what extent that is supported, especially with parametrization.

- B O E

Title: [SOLVED] Re: how to create an n-stage RC filter in Verilog-A
Post by sorgin1 on Feb 2^nd, 2012, 5:53am

Thanks BOE,

I was already using the genvar method, but missed a couple of other things.

I managed to get it working even including the parameterized number of stages. The following code shows the working model, at least for smartspice.

Code:

`include "discipline.h"

module rc_ladder(in, out, gnd) ;
inout in,out,gnd;
electrical in,out, mid,gnd;

parameter r=1k ;
parameter c=1n ;

analog begin
// stage 1
I(in,mid) <+ V(in,mid) / r;
I(mid,gnd) <+ ddt( V(mid,gnd) * c );

// stage 2
I(mid,out) <+ V(mid,out) / r;
I(out,gnd) <+ ddt( V(out,gnd) * c );
end
endmodule

// parameterized version using a for loop with genvar

module rc_ladder_forloop(in, out, gnd) ;

parameter integer steps = 2;

inout in,out,gnd;

electrical [0:steps] con;
electrical in, out, gnd;

parameter r=1k ;
parameter c=1n ;

genvar k;

analog begin
for (k=0 ; k < steps ; k = k+1 ) begin
I(con[k],con[k+1]) <+ V(con[k],con[k+1]) / r;
I(con[k+1],gnd) <+ ddt( V(con[k+1],gnd) * c );
end
V(con[0],gnd) <+ V(in,gnd);
V(out,gnd) <+ V(con[steps],gnd);
end
endmodule

and the netlist should be as follows:

Code:

Test RC-ladder loops

.verilog "./test.vams"

v1 in 0 PWL(0 0 5u 10 20u 10)

** Uncomment only one of the following two lines
** First line: fixed 2 stage RC ladder
** Second line: parameterized n-stage RC ladder

*YVLG_ladder in out 0 rc_ladder
YVLG_ladder in out 0 rc_ladder_forloop steps = 2

.tran 1n 20u
.iplot v(out)

Title: Re: [SOLVED] how to create an n-stage RC filter in Verilog-A
Post by boe on Feb 3^rd, 2012, 6:28am

sorgin1 wrote on Feb 2^nd, 2012, 5:53am:

...
I was already using the genvar method, ...

Seems I answered a bit to quickly...

- B O E