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Measurements >> Phase Noise and Jitter Measurements >> PLL noise aware design flow (PLL wizard) questions
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Message started by lunren on Feb 6^th, 2012, 4:24pm

Title: PLL noise aware design flow (PLL wizard) questions
Post by lunren on Feb 6^th, 2012, 4:24pm

Hi All,

It is a bit long story. I will try my best to explain it clear. Thanks for your patience to read it through and give me some feedback.
Recently I tried to follow Cadence noise-aware PLL design flow (PLL Macro Model Wizard) to verify my design. (We got the PLL_workshop from Cadence already) I think I successfully extracted VCO (oscmm), pfd+cp (pllTTpfd_cp) models. Then in 1st step, I run pll bench. It doesn't lock, vtune keeps going up. I think maybe I need to swap Fref and Fcomp (though I knew it is not correct to do so) to see what will happen. It turned out that the loop locks and I got correct phase noise curve which matches my simulation results (combining block noise with matlab) very well.

My interests are to see power supply noise effects on phase noise. So in 2nd step, I re-run the simulation with VCO model "oscmm_vdd". However the loop doesn't lock. I swapped Fref and Fcomp back, it still doesn't lock and vtune keeps going up. Then I replaced VCO model with "oscmm" and tried to reproduce what I got in 1st step, however the loop can't get locked whatever I played with Fref and Fcomp. I replaced model pllTTpfd_cp with transistor design, it locks. So I think there is some problem with the extracted model of pfd+cp. I re-extracted the model for pfd+cp (flowing the flow), but the problem
doesn't get solved.

Then I paid more attention to how the pfd+cp model was get extracted. From the log file, I found that :
PFD-CP model parameters:
Iup_max=5.38213 uA
Idown_max=965.764 nA
uptr=705.426 ps
downtr=23.0264 ps
refdelay=647.335 ps
fbdelay=658.021 ps
dir=1
Vtrans=1 V.

To me, it seems the extracted model is not correct since Iup_max and Idown_max are not equal and the number is not correct (should be 100uA). Then I run simulation to extract the pfd+cp model for cell "pfd_cp_bench" provided by Cadence in library "PLL_workshop", what I got is:
Iup_max=662.46 uA
Idown_max=4.18422 mA
uptr=1.78008 ns
downtr=551.137 ps
refdelay=2.11229 ns
fbdelay=802.128 ps
dir=1
Vtrans=1 V.

It seems the extracted model have the same problem: Iup_max and Idown_max are not equal (I verified that the current should be 4mA). But the pll_bench from library "PLL_workshop" have no lock problem.

I am wondering why my pll model doesn't lock and how to deal with this problem. If you need more information, please let me know.

Thanks a lot.

Lunren