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Design >> Analog Design >> high gain (>100 dB) and low power op-amp topology ?
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Message started by gsensor on Feb 19^th, 2012, 8:00pm

Title: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Feb 19^th, 2012, 8:00pm

Hi guys,

I'm working with 0.13 um CMOS technology and a 2.5V power supply.

I'm looking for a high gain (>100 dB) op-amp topology for narrow band low frequency signals (DC to 10 kHz). Ideally, I'm looking for a simple topology consuming less than 50 uW and having high voltage swing, near rail-to-rail. Low input referred noise is also needed, but as I'm planning to use an auto-zeroing (or CDS) configuration, this specification could be alleviated.

I have searched in scientific publications for hours, but I still don't find what I need..Any simple topology in mind ?

Thanks !

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by raja.cedt on Feb 20^th, 2012, 12:27am

hello,
whats the application? better start with 2 stage with first stage cascode (if posb gain boosting) and 2nd stage common source amplifier, if you are not happy with gain go with another stage. At least while designing op amps you should start with some architecture and keep on adding some stuff to reach.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Feb 22^nd, 2012, 12:23pm

Hi Raja,

thanks for your response. Indeed, I will start with a standard folded cascode topology with gain boosted amplifiers. I will try to size my transistors in sub threshold operating region, to get low power and low input noise. Hope this will work !

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by Vladislav D on Feb 22^nd, 2012, 1:24pm

gsensor wrote on Feb 22^nd, 2012, 12:23pm:

A bit of advice.
Design gain boosting stuff at last step, but before current sources implementations. Gain boosting amplifiers must only increase DC gain and should not degrade high frequency response(settling, PM and so on). Current sources and active load in cascode stage (top PMOS and low NMOS) should be in strong inversion to maintain low noise and low offset performance. For low noise, transconductance of these guys should be as small as possible. Also, if these transistors in weak inversion, you have exponential current dependence on Vt... this is really bad for the offset.

Don't use more than 2 stage. You will be able to satisfy the requirements with two stage. If you are not, means you r doing something wrong.
good luck

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by mixed_signal on Feb 22^nd, 2012, 4:16pm

Vladislav D wrote
"Also, if these transistors in weak inversion, you have exponential current dependence on Vt... this is really bad for the offset. "

I think exponential relation hurts current and hence leads to current mismatch since I is exponential function of Vgs-Vth. But Vgs is Logarithmic function of I. So, offset should not be an issue in weak inversion.

Can anybody suggest me how to add qotation to some line in previous posts?

Thanks

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by Vladislav D on Feb 23^rd, 2012, 1:02am

mixed_signal wrote on Feb 22^nd, 2012, 4:16pm:

For differential pair this is not an issue but for a current mirror it is

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 5^th, 2012, 3:44pm

Hi,

thanks for your advices everyone. I'm a beginner in analog design and I tried to size my transistors for a first simulation run according to this (see attachment for schematic):

-Cascode transistors (T0-T1) with minimal length and weak inversion to have high gm.
-Current sources (T4,T3,T5,T9) with small gm and strong inversion.
-High gm/id for diff pair (T6,T7) and cascode (T0,T1).
-Low power : Ibiais of 3 uA to get less than 25 uW.

Using simple calculations and couple of Spectre simulations, I got the design showed in attachment.

For some reason, when I simulate the open loop gain with Vcm = Vdd/2=2.5/2=1.25V and this equation : dB20((VF(''/vout'')/VF(''/vin+'')) in Spectre calculator tool, I get a DC gain of -40 dB, while hand calculations with experimental values gives me 53.3 dB, using this equation:
Av = (gmT6,T7 *gmT0,T1 *gmT5,T9) / (Ibiais^2 *(gmT0,T1*lambda_n^2 + gmT5,T9*lambda_p ) ) (from Dammak and al.)

Vin+ and Vin- are biased with AC =1 V and VDC=1.25V . What is going wrong ? Why it's not amplifying and what could I do to arrange this ?

Thanks a lot for your help,
gsensor

P.S: I'm using CMOSP 0.13 um with Vdd =2.5V

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 5^th, 2012, 3:49pm

Here's the attachment

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by Vladislav D on Mar 6^th, 2012, 1:33am

My friend, you should fix a DC biasing of your amplifier first. Hint: use a feedback

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by RobG on Mar 6^th, 2012, 7:08am

Vladislav D wrote on Feb 23^rd, 2012, 1:02am:

mixed_signal wrote on Feb 22^nd, 2012, 4:16pm:

For differential pair this is not an issue but for a current mirror it is

This is a bit confusing, so I'll restate what I think Vladislav meant.

Offset of the opamp will be ΔV_T(diff) + ΔV_T(mirrorp)*g_m(mirrorp)/g_m(diff) + ΔV_T(mirrorn)*g_m(mirrorn)/g_m(diff), where mirrorp and mirrorn indicate the pmos and nmos mirrors of the folded cascode opamp.

ΔV_T(diff) decreases as the square root of the area and has nothing to do with operating point. It could be significant if the sizes are small.

Note that the other terms are multiplied by the ratio of g_ms. If the diff pair gm is less than the mirror gm the V_T mismatch from the mirror is actually amplified. This is why you want to operate the mirror in strong inversion - i.e make gm g_m(mirror) small compared to g_m(diff). (This results in vdsat as large as possible, which unfortunately means an accurate mirror requires a lot of headroom.)

Noise follows the same principles.

The net result of all this is that you want to make your diff pair W/L ratio large, and the length of the mirror devices as large as you can. (It isn't obvious at first, but it turns out making the mirror devices wider does not help.) This definitely means the mirror should be operated in strong inversion and the diff pair in weak inversion if noise noise or offset is important.

Oh crap, I wrote all this and then remembered the OP is using CDS to null offset. Never mind >:( >:( >:( >:( ;D However, doing all this will minimize thermal noise which might be an issue, and it really should be how you design any opamp even if you *think* you don't care about these things.

I'm afraid the folded cascode topology might not give you the "near rail-to-rail" performance you require. If that is the case I would do a simple two stage amplifier with Ahuja-type compensation. Standard Miller compensation could also be used. The noise and offset minimization principles I just explained apply to any opamp topology, and IMO are about the most important design consideration in opamp design.

rg

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by Vladislav D on Mar 6^th, 2012, 7:32am

RobG wrote on Mar 6^th, 2012, 7:08am:

I'm afraid the folded cascode topology might not give you the "near rail-to-rail" performance you require. If that is the case I would do a simple two stage amplifier with Ahuja-type compensation. Standard Miller compensation could also be used. The noise and offset minimization principles I just explained apply to any opamp topology, and IMO are about the most important design consideration in opamp design.
rg

Yep, the important point, but why not to use the CMOS input pair?
And how can the "simple two stage amplifier" has higher CM range than folded-cascode?

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 6^th, 2012, 8:56am

Vladislav D wrote

Quote:

My friend, you should fix a DC biasing of your amplifier first. Hint: use a feedback.

I'm not sure I understand what you mean by DC biasing my amplifier first, isn't it what I'm already doing with the two VDC sources on vin+ and vin- ? What's the purpose of using a feedback configuration ?

Thank you.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by RobG on Mar 6^th, 2012, 9:11am

Vladislav D wrote on Mar 6^th, 2012, 7:32am:

Yep, the important point, but why not to use the CMOS input pair?

I don't understand... I never said anything about not using a CMOS diff pair. He should use one for sure.

Quote:

And how can the "simple two stage amplifier" has higher CM range than folded-cascode?

Just to be clear, we are talking output swing, not input common mode. The reason a folded cascode opamp does not have "rail-to-rail" swing is because the output of a folded cascode amp is a cascoded device, thus it needs more than Vdsat_(mirror) + Vdsat_(cascode) headroom. Furthermore, Vdsat_(mirror) should be relatively large to minimize noise (as I just explained). You generally can't get closer than 300-400 mV from either rail with a folded cascode without affecting the performance.

On the other hand, the two stage amp has non-cascoded output devices and the Vdsat of the output devices can be much smaller. You can even run the output devices in subthreshold without affecting the noise or offset.

Of course build a two stage amplifier with the folded cascode as the first stage if you need the gain.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 6^th, 2012, 10:50am

Ok, I just didn't put an AC voltage difference between vi+ and vin-..
I have an open loop gain of 58 dB which is consistent with my calculations..

Small question: If I change my Input common range to 1V (instead of Vdd/2 = 1.25 V), my DC gain lowers to 40 dB. Is this because my input common range is too small ?

Thanks RobG for your advice on low noise design, I will use them to reduce flicker and thermal noise to the maximum, even thought I might also use a CDS or auto-zeroing setup. Apparently, these techniques can only cut your noise by five times, and I want to achieve less than 70 nV/sqrt Hz at 1 Hz.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by Vladislav D on Mar 6^th, 2012, 12:33pm

OK, RobG. I misunderstood you because my first association with the "simple two stage amplifier" is a differential pair and the second stage is a transistor with active load. I think, gain >100dB is hardly feasible with this topology.

It is not clear what is a closed loop configuration. If the CMOS input pair will be used, the summing point is needed and so this is a folded cascode, anyway.

Quote:

Just think about how you are going to set the correct voltage at the nodes when the open-loop gain will be, say, 120dB. You need the feedback only at DC.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by loose-electron on Mar 7^th, 2012, 4:59am

A much more fundamental question:

Why so much gain?

I am trying to think of any case where
I have ever needed more than 80dB of gain.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 8^th, 2012, 9:04am

Hi loose-electron,

I need to have a high gain to keep the value applied to vin+ equal as much as possible to vin-, as this could affect my sensor's measures. I also have noticed from published work that most of high gain op-amps are used in ADC or DAC to have a high precision.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by loose-electron on Mar 8^th, 2012, 9:34am

differential pair input mismatch will become an issue long
before the systematic error associated with
a "non infinite gain" op-amp.

Generally, the approach taken is to find a way
to zero out offsets and other systematic errors.

That huge gain is probably not needed, or
becomes unimportant due to other sources of error.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 8^th, 2012, 12:31pm

Ok, thanks Loose-Electron.
Is there a way to lower the differential pair input mismatch from the beginning of the design (schematic), or only layout techniques can have an effect ?

I have follow RobG and Vladislav D advices in order to reduce the noise and the offset of my folded cascode opamp, essentially:

- High length, low gm and saturation operation for current mirrors.
- High gm, high length and sub-threshold for input differential pair.

I have a high gain (87 dB) but also a very high offset: 272 mV (Measured by connecting the non-inverting input to GND and the inverting input in feedback configuration to Vout, Vout = Voffset).

I have noticed that keeping the cascode transistors in subthreshold contributed to the high offset considerably, so I kept them in saturation, giving offset = 272 mV, instead of 364 mV. Lowering the wide of input differential pair had also a positive effect on lowering the offset.

I tried to lower gm of mirror NMOS and PMOS as much as possible to keep a high gain (at least 80 dB) and maintain them in saturation. I have no clue how to lower this offset more. Is there something I'm doing wrong that I can't see ??

(schematic, gain/phase, and output simulations are attached)

Thanks,
your help is very appreciated.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by RobG on Mar 8^th, 2012, 1:36pm

gsensor wrote on Mar 8^th, 2012, 12:31pm:

- High gm, high length and sub-threshold for input differential pair.

I think you mean "high width" for the diff pair.

You have something biased or sized incorrectly if you are seeing 272 mV of offset. With 87 dB open loop gain your simulated offset should be less than 100 uV unless you are running Monte Carlo or another mismatch analysis. Check the operating point of the devices.

I don't have time to untar your file. If you post a png or other graphic file we could all take a look at it.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 8^th, 2012, 1:48pm

yes, sorry high width..
ok Thanks, here's the schematic

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 8^th, 2012, 1:49pm

output swing :

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by RobG on Mar 8^th, 2012, 2:36pm

That operating point shows zero offset and the other plot looks normal. I'm not sure why you had more offset in the unity gain configuration.

edit... I now see the input is connected together so of course the offset is zero.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 8^th, 2012, 7:37pm

yes, sorry, I should have told you that the configuration in the folded cascode schematic I posted was to test the open loop gain.

Indeed, I used a unity gain configuration to test the offset (right configuration on following image).

To the the output swing, I varied vin+ from -200 mV to 200 mV, and plotted the output voltage (vout) vs vin+ by using the left configuration on the following image.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by RobG on Mar 8^th, 2012, 8:22pm

Put the Vin+ input at midrail, not at 0 volts. The output can't pull itself all the way down to the bottom rail.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by loose-electron on Mar 9^th, 2012, 7:24am

RobG wrote on Mar 8^th, 2012, 8:22pm:

Put the Vin+ input at midrail, not at 0 volts. The output can't pull itself all the way down to the bottom rail.

Agreed.

In addition

-- you need to estimate your offsets with real expected mismatches of your devices.
-- you need to size your transistors to get best matching available
-- you need to common centroid you matched sets of transistors

With all that you need to then determine
what your offsets will be with those things in place.

If you need better offset performance then you need to incorporate additional methods

-- static offset calibration methods
-- chopper methods to cancel offsets

Both would work

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 9^th, 2012, 10:12am

For the offset measurement, I have put Vin+= 0V following the definition of what's an offset voltage: "if differential input voltage of ideal op-amp is zero, the output voltage is also zero. In real op-amp, there is an offset voltage..."

I'm not sure to understand what's the relevance of using vin+= 1.25 V instead..ain't my output suppose to be able to go all the way down to the bottom rail ?

Anyway, if I use vin+=1.25V, I have vout = 1.258535 V, so I guess my offset is 8.535 mV (without using a mismatch process analysis) ? :

Also, according to my output swing simulation, the output swing is 0.505 V to 2.21 V ? Why doesn't my transfer curve hit 0V at the bottom ?

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by RobG on Mar 9^th, 2012, 6:24pm

gsensor wrote on Mar 9^th, 2012, 10:12am:

Also, according to my output swing simulation, the output swing is 0.505 V to 2.21 V ? Why doesn't my transfer curve hit 0V at the bottom ?

Because T0 and T10 go linear, thus the amount of current they sink for the same gate voltage decreases. As they become more linear eventually they won't be able to overcome the PMOS current sources and the output will pull down no further.

You need to keep the output devices out of the linear region if you want good performance (i.e. high open loop gain).

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by loose-electron on Mar 10^th, 2012, 12:48pm

as a general rule you do not want o operat the device near ground, or near the power supply.

You can design what is called a "rail to rail" (Power to ground) operational device,
but that will require extra circuitry.

I do agree with what RobG has said,.

Title: Re: high gain (>100 dB) and low power op-amp topology ?
Post by gsensor on Mar 12^th, 2012, 9:45am

Ok, thanks a lot for your explanations and advices guys ! It helps a lot !

As RobG suggested me earlier, I will use a simple second-stage with Ahuja compensation to achieve the near rail-to-rail output swing I'm seeking.

RobG wrote on Mar 6^th, 2012, 7:08am: