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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Physical Verification, Extraction and Analysis >> Difference between N/P –select and n/p - active layers in CMOS layout techniques https://designers-guide.org/forum/YaBB.pl?num=1330069699 Message started by VINAY RAO on Feb 23rd, 2012, 11:48pm |
Title: Difference between N/P –select and n/p - active layers in CMOS layout techniques Post by VINAY RAO on Feb 23rd, 2012, 11:48pm Hi, What is the significance of using n/p select layers along with n/p active layers to make a CMOS active device? Why we need to draw extra n/p select layers though we can distinguish P and N regions just by using P/N active regions? Regards, Vinay Rao. |
Title: Re: Difference between N/P –select and n/p - active layers in CMOS layout techniques Post by Geoffrey_Coram on Feb 24th, 2012, 7:29am This isn't a simulator question. Perhaps you should have posted it in "Physical Verification, Extraction and Analysis" ? |
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