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Design >> Analog Design >> sensitivity to source inductance of an LDOin dropout
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Message started by rajdeep on Mar 7^th, 2012, 9:06am

Title: sensitivity to source inductance of an LDOin dropout
Post by rajdeep on Mar 7^th, 2012, 9:06am

HI Guys,

I am having some problem with an LDO that seems to be oscillating when in dropout region. This I observe for the LDO that is inside the die, close to the center of the die. The LDOs (same core as the other one) which are at the edge are fine! It appears that it is the extra routing in the PCB from the input supply (VDD) to reach the vins of the center LDO causing the trouble, as the one at the edge is fine. Problem is I cant reproduce it in sims. I have to put an abnormally high (70nH) inductance to the VIN line with a 10uF bypass cap at VIN to form a tank-ckt to make it oscillate. But I dont think it is what I see exactly in the bench. I have been told by some of my group's experienced (>10yrs) designers that they have seen this before, and it is because of source inductance at the VIN side of the LDO.

The LDO core is classical PMOS pass-device one. The compensation is not so classical, as Rincon-moras LDO, i.e. dominant pole is NOT set by the load pole, if that is any useful info!

Has anybody experienced this before? Pls. throw some light into this inductively induced darkness then! :-[

Dropping off!
Rajdeep

Title: Re: sensitivity to source inductance of an LDOin dropout
Post by RobG on Mar 7^th, 2012, 12:17pm

Since distance seems to be the key, it might be metal bus resistance, either on the output or on the supply. Under some circumstances resistance on the supply can make the circuit unstable. It can also cause it to be coupled with other circuits.

Also, resistance in series with the load cap can put a zero in "too soon" which could cause issues. Metal resistances in modern processes is surprisingly high. I was also surprised at how important the sidewall capacitance is these days.

rg

Title: Re: sensitivity to source inductance of an LDOin dropout
Post by lunren on Mar 7^th, 2012, 11:27pm

Better to check extracted simulation (especially including routing resistance) with wirebond model (inductor, capacitor and resistor). If the loading current is too high and the input routing is long, the voltage drop across the input routing resistor will make the design very hard and some time becomes impossible.

Title: Re: sensitivity to source inductance of an LDOin dropout
Post by raja.cedt on Mar 8^th, 2012, 1:28am

hello,
fine i agree with all, but one cath here is why can't you make o/p pole dominate so that most of the switching current wil be by passed by decap!!. As robg pointed out in this junk lower technologies metal res is very high but i am pretty sure you wil be catch in extraction. Now Question is how you have bond wire inducatnce is same for every LDO on the die, becaz wether LDO is sitting centre or edge bond pad will be at the edge. So only res is matter i guess!!!

Title: Re: sensitivity to source inductance of an LDOin dropout
Post by rajdeep on Mar 8^th, 2012, 6:13am

Hi All,

Thanks for your reply guys. Extracted simulation is undoubtedly a good idea. Although I think the difference is because of the PCB layout, rather than the differences in the layout of the chip, it's worth trying! I have done some hand calculation depending on the layout and put them in schematic. But, yes cant be as accurate as the extracted one. Point on sidewall-cap is interesting.

Raja, I can do that, but unfortunately cannot do an all layer change, only metal edits. This is a usmd package where the center ones are accessed via extra vias, whereas the one at the edge are accessed directly. So the inductance could be different. But yes, whether it is the trace inductance, or also some mutual inductance are troubling, or the parasitic resistors, I am not 100% sure, but my (influenced by the popular gospels in our grp) hunch it's the slight increase of distributed inductance without much of real evidence really!

Just out of interest, why do you say that making dominant pole based on output pole would help here? In dropout when the pass-tr enters linear region, the o/p impedance drops quite a lot, and in which case can screw up the compensation even more, isnt it? Having said that, the overall loop gain drops, so that may help stabilizing the system.

Thanks!
Rajdeep