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Simulators >> AMS Simulators >> Dout looks HiZ for E2L_2_inhconn
https://designers-guide.org/forum/YaBB.pl?num=1333257097

Message started by ywguo on Mar 31^st, 2012, 10:11pm

Title: Dout looks HiZ for E2L_2_inhconn
Post by ywguo on Mar 31^st, 2012, 10:11pm

Hi Guy,

It is weird that Dout is always kept HiZ during the simulation.

The code is almost the same as that E2L_2_inhconn in built-in connectLib. I paste the code in the following.

Code:

// INCLUDE FILES:
`include "disciplines.vams"
`timescale 1ns / 100ps

//============================================================================
connectmodule E2L_2_inhconn (Ain, Dout);
input Ain; electrical Ain; // electrical input
output Dout; \logic Dout; // logic output

// Inherited vdd! and vss!
electrical
(* integer inh_conn_prop_name="PVDD";
integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ;
electrical
(* integer inh_conn_prop_name="NVSS";
integer inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ;

// INSTANCE PARAMETERS:
parameter real tr=0.2n from (0:1m); // risetime (for defaults)
parameter real txdel=4*tr from (0:1m); // time midrange til output X
parameter real ttol_c=tr/4 from (0:1m); // time tolerance of crossing
// scaled input/output levels/thresholds (0 maps to Vref, 1 maps to Vsup):
parameter real vthi=1/1.5 from (0:1); // frac. for high tresh (def=2/3)
parameter real vtlo=vthi/2 from (0:vthi); // frac. for low tresh (def=1/3)
parameter real vtol=1.0/12 from (0:(vthi-vtlo)/2]; // frac. for vtol
parameter real vtlox=vtlo+vtol from (vtlo:vthi); // lo to X state threshold
parameter real vthix=vthi-vtol from [vtlox:vthi); // hi to X state threshold

// LOCAL VARIABLES:
reg Dreg; // output register
reg Xin; // Tx control registers
real Kin; // input relative to supply range
real txdig; // tx in timescale units

//============================================================================
initial begin
txdig=txdel/1n; // digital delay midlevel to X (ASSUMES TIMESCALE)
Dreg=1'b0; // initial level
Xin=0; // initially not in X delay region.
end

// Relative input level (maps input to range of 0=vref, 1=vsup):
analog Kin = V(Ain,\vss! )/max(V(\vdd! ,\vss! ),1m);

// Convert analog signal to high/low and X/notX:
always @(above(Kin-vthi,ttol_c,vtol))
begin Dreg=1; Xin=0; end // analog XtoH
always @(above(vtlo-Kin,ttol_c,vtol))
begin Dreg=0; Xin=0; end // analog XtoL
always @(above(vthix-Kin,ttol_c,vtol))
if (Dreg==1'b1) Xin=1; // analog HtoX
always @(above(Kin-vtlox,ttol_c,vtol))
if (Dreg==1'b0) Xin=1; // analog LtoX
// Wait for txdel before driving output to X:
always @(posedge(Xin)) begin // input changed to X
#(txdig) // wait for X time delay
if (Xin==1) Dreg=1'bx; // goto X if still between
end
assign Dout=Dreg; // assign register to output
always @(Dout) begin
$display($time, "\t Dout = %1b \n", Dout);
end
always @(Dreg) begin
$display($time, "\t Dreg = %1b \n", Dreg);
end

endmodule

The always block @(Dout) and @(Dreg) are for monitoring the toggle of Dout and Dreg. It is curious that Dout is always HiZ although Dreg toggles.

My tools are IC6.1.4.500.10, and MMSIM 11.1.0.249.isr2, and INCISIVE 10.20-s043.

Any comments are appreciated.
Yawei

Title: Re: Dout looks HiZ for E2L_2_inhconn
Post by ywguo on Mar 31^st, 2012, 10:30pm

The following is part of irun.log.

Code:

errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS

1 Dreg = 1

tran: time = 3.04 ns (3.04 %), step = 779.9 ps (780 m%)
5 Dreg = 0

tran: time = 7.559 ns (7.56 %), step = 133.7 ps (134 m%)
9 Dreg = 1

tran: time = 12.95 ns (12.9 %), step = 554.1 ps (554 m%)
14 Dreg = 0

tran: time = 17.67 ns (17.7 %), step = 554.7 ps (555 m%)
18 Dreg = 1

22 Dreg = 0

tran: time = 22.73 ns (22.7 %), step = 480 ps (480 m%)
26 Dreg = 1

tran: time = 27.68 ns (27.7 %), step = 772.9 ps (773 m%)
30 Dreg = 0

tran: time = 32.56 ns (32.6 %), step = 133.6 ps (134 m%)
34 Dreg = 1

tran: time = 37.95 ns (37.9 %), step = 554.1 ps (554 m%)
39 Dreg = 0

tran: time = 42.67 ns (42.7 %), step = 554.7 ps (555 m%)
43 Dreg = 1

47 Dreg = 0

Title: Re: Dout looks HiZ for E2L_2_inhconn
Post by boe on Apr 2^nd, 2012, 11:53am

Ywguo,
Is the power supply OK? I remember seeing some very weird behavior without power (although I think it was an L2E-CM).

- B O E

Title: Re: Dout looks HiZ for E2L_2_inhconn
Post by ywguo on Apr 8^th, 2012, 7:25pm

B O E,

I looked at the simulation again. The supply is OK, otherwise the circuitry malfunctions. Although Dout in E2L_2_inhconn is HiZ, the succeeding verilog modules (inverters and DFFs) work very well. :(

Best Regards,
Yawei

Title: Re: Dout looks HiZ for E2L_2_inhconn
Post by rsmithuf on May 22^nd, 2012, 8:45am

I am also having this problem with the Dout of E2L's staying HiZ although Dreg is toggling. I am using the E2L_0 builtins. Was there any resolution or clue to this?

Thanks!

Title: Re: Dout looks HiZ for E2L_2_inhconn
Post by ywguo on May 22^nd, 2012, 6:36pm

Hi rsmithuf,

I have not making any progress in this problem. :(

Best Regards,
Yawei

Title: Re: Dout looks HiZ for E2L_2_inhconn
Post by rsmithuf on May 23^rd, 2012, 11:20am

So I find that when I probe the E2L's internal signals (Dout, Ain, etc) the Dout is always 'Z'. However, if you look at the cell that this signal is connected to, it is properly resolving to a '0' or '1' depending on the connect rules used.