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Simulators >> RF Simulators >> PLL phase margin with PSS/PSTB ?
https://designers-guide.org/forum/YaBB.pl?num=1334078890

Message started by ellarguero on Apr 10^th, 2012, 10:28am

Title: PLL phase margin with PSS/PSTB ?
Post by ellarguero on Apr 10^th, 2012, 10:28am

dear all,

i want to simulate the phase margine of a voltage domain behavioral model of PLL using PSS/PSTB.
i got strange results though:

here is my schemativ annotated my components

time domain simulation works well (strobed)

but when i do pss/pstb i get strange results depicted below

i insert the probe between the loop filter and the vco
i don't know what's going wrong
please help me figuring out what's wrong

Title: Re: PLL phase margin with PSS/PSTB ?
Post by ellarguero on Apr 10^th, 2012, 12:32pm

dear all,
i added a pac analysis, the transfer function from the reference source to the output dff is -6.4K dB which means the loop is open !!!!
from where may come this probleme, i thought pss take care of the different states of the pfd

Title: Re: PLL phase margin with PSS/PSTB ?
Post by Frank Wiedmann on Apr 11^th, 2012, 1:21am

I suggest you take a look at http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426.

Title: Re: PLL phase margin with PSS/PSTB ?
Post by ellarguero on Apr 11^th, 2012, 9:21am

Thank you Frank,

What i conclude from the thread you gave is that the models should be smooth, i use transition filter in each of my verilog-a sources and i set both fall and rise times to 1/100th of the period. i think it's smooth enough
but the probleme still shows up
from where can come this probleme

Title: Re: PLL phase margin with PSS/PSTB ?
Post by Frank Wiedmann on Apr 11^th, 2012, 1:19pm

Look for the pac signal at all the nodes in your circuit and see where it disappears.