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Design Languages >> VHDL-AMS >> For loop
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Message started by Eng.nihal on Apr 15^th, 2012, 9:04am

Title: For loop
Post by Eng.nihal on Apr 15^th, 2012, 9:04am

how i can solve the problem of 1 clock cycle of for loop if i want that each input start in a clock not all the inputs take one clk cycle???

thanks in advance