The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> High-Speed I/O Design >> Understanding differnce bw Phase Slew Rate and Jitter Tolerance
https://designers-guide.org/forum/YaBB.pl?num=1342774193

Message started by Mayank on Jul 20^th, 2012, 1:49am

Title: Understanding differnce bw Phase Slew Rate and Jitter Tolerance
Post by Mayank on Jul 20^th, 2012, 1:49am

Hi,

I have a doubt regarding difference bw 2 different specification quoted in USB3.0, Phase Slew Rate and Jitter Tolerance.

It says that Digital Clock Recovery ckts have a certain phase slew rate limitation - given by Phase update rate * Step Size. --> Understandable.

Q1. Won't analog CDRs have a limited slew rate ?
Q2. If we are obeying a certain JTOL, does that mean I am obeying a Slew rate limit equal to a -20dB/dec slope line passing through the corner point of the JTOL curve. [corner point = where JTOL curve becomes flat]

Q3. If slew rate -20dB/dec line is above JTOL, does it mean I have to design a CDR with jitter tolerance equal to the limit from Slew rate spec ?

--Mayank.

Title: Re: Understanding differnce bw Phase Slew Rate and Jitter Tolerance
Post by BackerShu on Jul 31^st, 2012, 1:05am

Hi Mayank, very interesting question.

For digital implementation, as you said, it is understandable since the maximum phase update rate is somewhat a fixed value, which is depended on the proportional path gain. This paper has a pretty good explanation on it; just in case you haven't checked this paper yet.
[1] R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” pp. 1–12.

For the analog CDR, I am not exactly sure. Here are my understandings to your three questions:

Q1: Yes, I think so, and the Phase Slew Rate is decided by the maximum speed charge pump can charge the capacitor in loop filter. In other words, it should related to Icp/sC.

Q2: Again, theoretically I think so, but this would be the minimum requirement of Phase Slew Rate to certain meet JTOL requirement. Some margin is necessary.

Q3: I am not sure what do you mean here. If you are still think about meeting the JTOL requirement, reduce the Slew Rate would be better since it will save some power.

Correct me if I am not right.

Title: Re: Understanding differnce bw Phase Slew Rate and Jitter Tolerance
Post by depend135 on Oct 22^nd, 2012, 8:29am

Hi, Backer,

I think for the first question, it depends on the type of the phase detector. For the analog CDR with a bang-bang PD, it also has a limited phase slew rate which is controlled by the propotional path and is not related to the loop filter capacitor.

For the CDR which uses a linear PD, its phase tracking speed is limited by the bandwidth instead of slew rate since its output phase is not slewing.

What is your thought?

Dep

Title: Re: Understanding differnce bw Phase Slew Rate and Jitter Tolerance
Post by BackerShu on Nov 15^th, 2012, 11:32am

depend135 wrote on Oct 22^nd, 2012, 8:29am:

...

For the CDR which uses a linear PD, its phase tracking speed is limited by the bandwidth instead of slew rate since its output phase is not slewing.

What is your thought?

Dep

Agree with you!
As long as the phase error is within the range of liner PD， the update rate is governed by bandwidth.

Thanks for clarifying this point.