The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Other CAD Tools >> Physical Verification, Extraction and Analysis >> questions about extract layout with calibre
https://designers-guide.org/forum/YaBB.pl?num=1343994374

Message started by easyads on Aug 3^rd, 2012, 4:46am

Title: questions about extract layout with calibre
Post by easyads on Aug 3^rd, 2012, 4:46am

Hi
I use calibre 2007 to extract layout. The layout is under tsmc 0.18um process.
But I found there is some problem. Assuming that there is a mimcap between A and B. After the extraction, the mimcap between A and B is extracted out. But also another pararistic capacitor whose value is about equal to the value of mimcap is extracted between A and B . So the capactior is about doubled for mimcap after extraction.
How can I solve this problem? Should I change the setup of calibre or change the version of value? Should I change the command file of extration?
Thanks

Title: Re: questions about extract layout with calibre
Post by Maks on Aug 11^th, 2012, 5:37pm

To avoid extracting parasitics (R, C) that are accounted for in compact (SPICE) models, parasitic extraction tools are doing "device blocking" - i.e. de-embedding devices, or ignoring parasitic elements associated with "intrinsic" device properties.

If device blocking is not defined properly in the extraction rule deck - bad things can happen, for example - capacitance of MIM or MOM capacitor will be counted twice (1. in parasitic extraction and 2. in compact model).

That being said - most likely Calibre extraction rule deck is not including MIM capacitor layers in its stack, and thus is not extracting plate-to-plate capacitance - please check your Calibre deck...