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Modeling >> Behavioral Models >> Modelling of a simple counter in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1349190325

Message started by radius2 on Oct 2^nd, 2012, 8:05am

Title: Modelling of a simple counter in Verilog-A
Post by radius2 on Oct 2^nd, 2012, 8:05am

Hi,

I'm trying to model a simple counter in Verilog-A. The counter should simply count the number of positive clock edges of the input signal Clk.
I wrote the following code to model the behaviour:

@(cross(V(Clk)-Vtreshold, +1)) begin
count = count + 1;
$strobe(count) //prints the value of the count variable

I simulated the counter in spectre for 5 clock cycles and hoped to
see the variable count printed out 5 times and increased to 5. However, it increased to about 100. It seems as the statements inside the @cross are evaluated several times when the crossing is detected.
I guess that I missunderstood the crossing function. Is there a way to
only detect the clock edge only once when the crossing is detected?

Title: Re: Modelling of a simple counter in Verilog-A
Post by Geoffrey_Coram on Oct 2^nd, 2012, 8:30am

The cross function works OK for me.

I would suggest you put
$strobe("crossing detected at %g, count now %d", $abstime, count);
inside the cross event block, and see if you get the message multiple times for a particular $abstime -- and if the time values correspond to when you think the crossings should occur.

Title: Re: Modelling of a simple counter in Verilog-A
Post by radius2 on Oct 4^th, 2012, 10:07am

Hi,

Thank you for your reply.
I've fixed it now.

Title: Re: Modelling of a simple counter in Verilog-A
Post by Geoffrey_Coram on Oct 10^th, 2012, 2:42pm

It's usually nice to say what you fixed, for the benefit of other readers, or someone who searches the forum later and has the same problem.

Title: Re: Modelling of a simple counter in Verilog-A
Post by radius2 on Oct 11^th, 2012, 5:43am

Off course,

I think the problem was that I first copied the code from another
cell and forgot to change the module declaration. The module declaration was

module CellX(In, Out, Clk)

instead of

module Counter(In, Out, Clk),

while the name of the cell is still Counter.

As the code refers to another already existing module it will
cause strange behaviour. An advice is therefore to always check this
when finnished with the code.