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Modeling >> Behavioral Models >> Modeling of Frequency divider - Cadence SpectreRF
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Message started by nikgr on Oct 20^th, 2012, 1:44am

Title: Modeling of Frequency divider - Cadence SpectreRF
Post by nikgr on Oct 20^th, 2012, 1:44am

Hi to everyone.

I have a VCO and I want to divide the frequency of the output signal by 2 and see through pss/pnoise analysis the phase noise of the divided signal. I want to use a behavioral model in Verilog-A. However I have problem with the starters, meaning:

First of all I saw that the simple counter doesn't work due to hidden states. So I saw the solution of frequency divider proposed by Ken Kundert for no hidden states, but it doesn't work neither because the output voltage is 0 volts.

Then i tried the D flip flop RF model proposed by Ken Kundert for no hidden states and I added a line that is the additional complementary output qc. I connected output qc with input d in order to have the classic divide-by-2 configuration.
The problem is that even transient analysis gives error: no DC solution found (no convergence).

If i don't have output qc connected to input d (D flip flop function only) the transient analysis runs ok. So there is a problem with the initial condition of the loop ouput qc - input d.
However if I don't have output qc connected to input d, pss analysis gives error: Matrix is singular (detected at `I15:idt0'). Perhaps something goes wrong with the integration used in the code?

Could you please suggest me what to do?

Thanks

Title: Re: Modeling of Frequency divider - Cadence SpectreRF
Post by Geoffrey_Coram on Oct 24^th, 2012, 5:45am

nikgr wrote on Oct 20^th, 2012, 1:44am:

So I saw the solution of frequency divider proposed by Ken Kundert for no hidden states, but it doesn't work neither because the output voltage is 0 volts.

Do you understand how that model is supposed to work? Have you tried debugging it? You can add lines like
$strobe("V(chg)=%d V(hold)=%g out=%g", V(chg), V(hold), out);
to see some of the internal workings.

A quick thought is: I noticed that Vdd=5 in his model, so if you're working with a 2.5V or lower supply, you'll never get above the threshold assumed by that model.