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Modeling >> Behavioral Models >> getting problem during simulation of sc integrator
https://designers-guide.org/forum/YaBB.pl?num=1351762116

Message started by sourav on Nov 1^st, 2012, 2:28am

Title: getting problem during simulation of sc integrator
Post by sourav on Nov 1^st, 2012, 2:28am

Hi
I am getting unexpected output while simulating a SC integrator using a verilog-a model of opamp. I have tested a SC inverting gain stage and got desirable output :). For that circuit I have discharged the feedback capacitor in each clock pulse.
But for integrator circuit we need to keep the charge of feedback capacitor. When I am doing not discharging the feedback capacitor I am getting :-/unexpected output(like in KV range as I am not using opamp saturation condition).

I think this is probably due to no feedback at DC. Can anyone suggest anything about the circuit :'(.

Thank you

Title: Re: getting problem during simulation of sc integrator
Post by ywguo on Jan 28^th, 2013, 6:32pm

HI sourav,

You said that the output was in kV range as the opamp did not have saturation condition. Did the opamp have soft limiting of output voltage?

If you post the code or block diagram of your opamp/sc-integrator, it maybe helpful for you to get fast response.

Best Regards,
Yawei

Title: Re: getting problem during simulation of sc integrator
Post by Ken Kundert on Jan 28^th, 2013, 10:40pm

Why don't you skip dc. If you are using Spectre, set the transient option skipdc=yes.

-Ken