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Modeling >> Semiconductor Devices >> leakage current in 65 nm CMOS Technology?
https://designers-guide.org/forum/YaBB.pl?num=1352087089

Message started by henrytqy on Nov 4^th, 2012, 7:44pm

Title: leakage current in 65 nm CMOS Technology?
Post by henrytqy on Nov 4^th, 2012, 7:44pm

Hi all,

I adopt a 100 pF MOS varactor (Area: 6000 um^2) in my ckt with the standard 65 nm CMOS Technology. But the simulation in spectre shows the leakage current is as large as 350 nA, which is too large and unaccepted to me.

my test bench is a simple RC low pass filter with only the DC excitation.

I don't know whether my test bench is correct or the leakage current is really at that level in 65 nm.

Thanks for your help~~~

Title: Re: leakage current in 65 nm CMOS Technology?
Post by Geoffrey_Coram on Nov 5^th, 2012, 5:42am

You should ask your foundry for measurement data; it's probably proprietary data, so others on this forum would not be able to share (even assuming the values were similar in all 65nm technologies).

Title: Re: leakage current in 65 nm CMOS Technology?
Post by henrytqy on Nov 5^th, 2012, 7:22am

Thanks~~~it is really at that order of magnitude.

Geoffrey_Coram wrote on Nov 5^th, 2012, 5:42am:

You should ask your foundry for measurement data; it's probably proprietary data, so others on this forum would not be able to share (even assuming the values were similar in all 65nm technologies).

Title: Re: leakage current in 65 nm CMOS Technology?
Post by Lex on Nov 14^th, 2012, 2:53am

Make sure your simulation is accurate enough, and check its dependency on bias voltage to be sure you're looking at the right thing.

Title: Re: leakage current in 65 nm CMOS Technology?
Post by raja.cedt on Nov 14^th, 2012, 3:57am

hello,
as every one said it depends on the fab, but 350nA looks really lesser than the published one. Please refer the following jssc pap, they have reported few numbers on leakage, for 900um^2 hey have 1mA leakage current.

http://www2.ee.ntu.edu.tw/~ecl/Professor/A%20Leakage-Current-Recycling%20Phase-Locked%20Loop%20in%2065%20nm%20CMOS%20Technology.pdf

Try to read some more from the same authors you will find few more interesting leakage numbers.

try to simulate in the following manner.
By applying 1V ac voltage source at the gate of cap and measure current through gate.

Thanks,
Raj.