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Simulators >> AMS Simulators >> Bind to schematic and verilog view for standard cells
https://designers-guide.org/forum/YaBB.pl?num=1354269418

Message started by ywguo on Nov 30^th, 2012, 1:56am

Title: Bind to schematic and verilog view for standard cells
Post by ywguo on Nov 30^th, 2012, 1:56am

Hello Guys,

I need to bind standard cell to schematic and verilog views simultaneously in my test bench. In one part of my design, it is implemented with RTL, syntheis, and PR. the other part of my design is schematic drawn manually. That is a good test bench in the early stage of my design. I can simulate RTL code and schematic with ams designer.

Now I have verilog netlist exported from PR tool, and related SDF file. I want to verify the function and timing of the analog/digital interface. It is good to simulate the test bench with verilog netlist + SDF for the digital part, and with transistors in the analog part.

Of course the standard cells in the digital part are bind to verilog view. Unfortunately, some standard cells are used in the analog part, too. The simulation stops and have the following error message.

Quote:

1779_1 (I1778_Y, dvdd, dgnd, clk_f);
|
ncelab: *E,CUVWLP (./netlist.vams,217|6): Too many module port connections.

It seems that ams designer does not clarify the verilog view and schematic view. The schematic view has two additional pins, vdd and vss, compared to the verilog view.

Anyone can help me? Do you have any comments? Thanks in advance.

Yawei