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Modeling >> Behavioral Models >> Settling time simulation with phase behavioral model of PLL
https://designers-guide.org/forum/YaBB.pl?num=1354716241

Message started by Yutao Liu on Dec 5^th, 2012, 6:04am

Title: Settling time simulation with phase behavioral model of PLL
Post by Yutao Liu on Dec 5^th, 2012, 6:04am

Hello everyone,
I have a problem when simulating settling time of PLL with phase behavioral model. I used a vcvs to model a divider and configured the voltage ratio as 1/N. I ran a transient simulation with N=64 at 0.1us and N=68 at 80us. But the simulation did not work and reported that the control voltage of VCO exceeded 1GV at t=10us. So the simulation was aborted.

First, I want to know whether my test-bench is all right.
Second, if my test-bench is OK, how to fix the problem?

Thanks,
Yutao

Title: Re: Settling time simulation with phase behavioral model of PLL
Post by raja.cedt on Dec 5^th, 2012, 10:08am

i guess fb is +ve by mistake, so please check the polarity.

Title: Re: Settling time simulation with phase behavioral model of PLL
Post by Yutao Liu on Dec 6^th, 2012, 5:07am

Hi raja,
Thanks for your reply. I connected the fb to the negative node in the vcvs which modeled the PFD. And the vco_output was connected to the positive node in another vcvs modeling the divider. The stb simulation reported an enough phase margin. So I was confused what destroyed the stability in transient simulation.

I tried to interchange the fb and fref, the transient simulation converged, but the result showed that Vctrl stayed at the same voltage no matter how the divide ratio N changed. I thought this is incorrect.

By the way, I made a mistake in my previous post. It was not Vctrl, but vco_output that exceeded 1GV at t=10us.

Do you have any idea?

Best,
Yutao

Title: Re: Settling time simulation with phase behavioral model of PLL
Post by raja.cedt on Dec 6^th, 2012, 8:40am

i am pretty sure problem with polarity, please provide a snap shoot some one can point out mistake easily....

Title: Re: Settling time simulation with phase behavioral model of PLL
Post by Mike A on May 7^th, 2013, 9:48pm

Hi,

just in case you are still interested and have not found a solution, you may want to check that the simulator is not giving you an 'exceeds BLOWUP limit' kind of warning.
This can happen as if you map the phase of the VCO to voltage, this increases of course indefinitely from t=0 at a rate given by your VCO's frequency. Even if the feedback is set correctly, still the absolute value of the voltage may trigger the simulator 'BLOWUP response', thus stopping it.

I had this specific issue, and I solved it in two - consecutive - ways

1 - I changed the BLOWUP limit to a higher value. This worked fine

2 - I did not like the idea of having extremely big numbers and other - important - much smaller numbers as outcomes in my simulation. So I built an ultra simple block in Verilog-A, which is wrapping the phase output to -2Pi to 2Pi

Hope this helps,

Michele