The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> DAC capacitive array issue in SAR ADC
https://designers-guide.org/forum/YaBB.pl?num=1355234878

Message started by Lissa on Dec 11^th, 2012, 6:07am

Title: DAC capacitive array issue in SAR ADC
Post by Lissa on Dec 11^th, 2012, 6:07am

I want to discuss an issue I am facing while working on the design of DAC capacitive array. For simplicity I have reduced the array to 3 bits only. The capacitive array in SAR ADC has to be driven by a switch . When capacitve array is driven by ideal pulse sources, capacitors charge to the right voltages. But when, in Fig , i replace one of the pulse sources with transmission gate switch (with input as 2.8 ref voltage-I am keeping Vref the same as Vdd for now) the resultant net charge on the capacitive array gets distorted although the switch yeilds 2.8Vat the output but it fails to drive the capacitors. What can be done to make switch drive this capacitive array as eventually I have to drive each capacitor on the array with a switch. Thanks

Title: Re: DAC capacitive array issue in SAR ADC
Post by Lissa on Dec 12^th, 2012, 8:49am

Actually the problem is related to SAR ADC design.......

Title: Re: DAC capacitive array issue in SAR ADC
Post by Lex on Dec 13^th, 2012, 1:35am

What do you mean by not being able to drive it? If your transmission gate is low, then the capacitor input is floating. The ideal voltage sources don't let the capacitor side float.

Title: Re: DAC capacitive array issue in SAR ADC
Post by Lissa on Dec 13^th, 2012, 7:17am

Thanks Lex for your reply. Actually I am designing SAR ADC which requires the design of DAC capacitive array. I am having problem with driving the capacitive array to store charge and raise the output node (top plate of capacitors combined together)to certain voltage, say 2V. Currently the maximum output the capacitive array generate is 0.6 v while the input signal i want to digitize swings between 0.7 to 1.8 V. I can level shift the input voltage but i need to increase the range of capacitive array. Is there any more information you need? Switches are driving the cap array but i have tried everything to come up with some promising resluts! Attached are few of the images of my work.....as you can see DAC cap array yields only 0.6V when all all bits are set!

Title: Re: DAC capacitive array issue in SAR ADC
Post by Lex on Dec 14^th, 2012, 12:50am

Can you show the complete schematics?

Title: Re: DAC capacitive array issue in SAR ADC
Post by dcic on Feb 20^th, 2013, 8:54pm

1. Make sure the ratio between adjacent caps are the radix that you intended to design
2. Typically if you see correct ratio between voltages steps but overall the DAC voltage is lowered, that means there is attenuation at the output of the DAC. That is, DAC is loaded by some external cap that changes the overall gain