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Analog Verification >> Analog Performance Verification >> pdf "A methodology for the offset-simulation of comparators"
https://designers-guide.org/forum/YaBB.pl?num=1355990149

Message started by weber8722 on Dec 19^th, 2012, 11:55pm

Title: pdf "A methodology for the offset-simulation of comparators"
Post by weber8722 on Dec 19^th, 2012, 11:55pm

Hi,

I like it a lot, but although it looks so nice and magic :), it can be improved quite easily. The major disadvantages of the method described in the pdf are:

- use of matlab for calculations
- some overhead in the simulation, e.g. ones the threshold is reached there is no need to waste time by still continuing the transient run
- the ramp resolution is quite limited, i.e. if you need very small steps to detect also a small hysteresis (like 10uV), you and up with long simulation times (e.g. the offset range should be often 100mV or so, resulting in 10,000 steps).
- the comparator behavior (like delay) also highly depends on the previous clk-cycle input voltage. In this testbench there is no flexibility on checking it. In the example the comp design is not really a good one, because the recovery behavior is bad due to missing clamps or reset circuitry (leading to big hysteresis)

VerilogA would offer all capabilities to get rid off all the problems. In Cadence standard tools there is a nice VerilogA module doing measurements e.g. threshold (or setup time) using transient analysis but not with a linear ramp, instead using the much faster bi-section method. I found the nice Cadence code :D in the DCM parts of ADEGXL, and modified it a bit (like offset output result not only to log file but as pin, up+down ramp to see hysteresis).

Bye Stephan

Title: Re: pdf "A methodology for the offset-simulation of comparators"
Post by Sun_ly on May 31^st, 2014, 2:39am

Hi:
I have read it. Find it is helpful.But I has some confuses.
In your example,I can't figure out why that comparator has hysteresis? Could you help me???