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Simulators >> AMS Simulators >> How to speed up simulation run time with VerilogA?
https://designers-guide.org/forum/YaBB.pl?num=1356279065

Message started by Idan Kligvasser on Dec 23^rd, 2012, 8:11am

Title: How to speed up simulation run time with VerilogA?
Post by Idan Kligvasser on Dec 23^rd, 2012, 8:11am

Hi,

Is there is a way to speed up the simulation run time when using VerilogA blocks? Can i used compiled folders instead of compiling every time?

Thanks!
idan

Title: Re: How to speed up simulation run time with VerilogA?
Post by sheldon on Dec 24^th, 2012, 5:58pm

Idan,

Compiling is only performed when there have been changes to the
model, that is, when it is required.

Sheldon

Title: Re: How to speed up simulation run time with VerilogA?
Post by Idan Kligvasser on Dec 27^th, 2012, 4:56am

thank you sheldon