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Analog Verification >> Analog Performance Verification >> transient/pss simulations with parasitic extracted netlist
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Message started by analog2000 on Dec 30^th, 2012, 1:05pm

Title: transient/pss simulations with parasitic extracted netlist
Post by analog2000 on Dec 30^th, 2012, 1:05pm

Hello,
I have a switched cap 4th order low pass filter which is differential in nature.
I can do transient/pss/pxf simulations without any problem on a netlist generated from a schematic.
However, I do not see any meaningful outputs when I try to simulate the same circuit using layout extracted parasitics (R+C).

The # of nodes is 31174, # of bsim3v3 is 2881, bourse_1 is 755, capacitors is 50100, resistors are 40022.
With this size netlist, the transients and the pss simulations do not start properly. The opamp outputs hit the rails, the moment the clocks start.

I read spectre.ic from readic menu, I use +parasitics and +csfe to minimize the # of parasitics.

Any help will be greatly appreciated

thanks
analog2000

Title: Re: transient/pss simulations with parasitic extracted netlist
Post by rfidea on Dec 30^th, 2012, 1:29pm

Two simple questions.

Does the DC operating point looks ok in the extraction sim? Specially the outputs from digital gates if you use such devices as clock drivers.

Is the layout LVS clean?

Title: Re: transient/pss simulations with parasitic extracted netlist
Post by analog2000 on Dec 30^th, 2012, 2:31pm

I am setting the initital conditions with a spectre.ic file that I created when doing transient on the schematic based net list earllier. I am setting skipdc=yes to force the simulator to use the ic on all relevant nets so dc op should not be necessary to run
Yes, the layout is lvs/drc clean
analog2000

Title: Re: transient/pss simulations with parasitic extracted netlist
Post by rfidea on Dec 31^st, 2012, 1:23am

Both pss and tran is doing a DC analysis before the actual transient analysis starts. The initial conditions is only used to set the initial "guess" for that DC analysis.

My idea about looking at a DC solution is to see if your circuit behaves as expected in DC. It not, there is some mayor fault.