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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Extracting board parasitics in Cadence virtuoso environment
https://designers-guide.org/forum/YaBB.pl?num=1359373528

Message started by rajdeep on Jan 28^th, 2013, 3:45am

Title: Extracting board parasitics in Cadence virtuoso environment
Post by rajdeep on Jan 28^th, 2013, 3:45am

Hello All,

I guess this has been discussed before, but could not find it, so decided to ask it here.

Is there a way we can extract board parasitics from Altium schematic/layout (preferably layout) in some format (like Cadence Spectre, spice, verlogA etc.) so that it can be used for chip level simulations using Cadence Spectre (or AMS)?

I have come to know that Cadence does support this if the layout was done in Cadence Allegro, but we are stuck with Altium.

If anybody can share some docs/pdfs on this flow will be much appreciated.

Thanks,
Rajdeep

Title: Re: Extracting board parasitics in Cadence virtuoso environment
Post by raja.cedt on Jan 28^th, 2013, 4:31am

Hello,
If you have ads momentum, simulate S parameters and use nport in cadence.

Thanks,
Raj.

Title: Re: Extracting board parasitics in Cadence virtuoso environment
Post by rajdeep on Jan 28^th, 2013, 6:08am

Hi Raj,

Thanks for the reply. Our board designs are done in Altium only. So looking for a way of back annotation that starts from Altium layout/schematic.

Thanks
Rajdeep