Title: Phase margin of a behavioral OPAMP model
Post by ywguo on Jan 28th, 2013, 6:26pm
Hi Guys,
I have a OPAMP model. To my surprise, it has 74 degree phase margin if I set GBW = 10MHz while it is 17 degree phase margin if GBW=1GHz.
Since the code is too long to be accommodated in one post, I put it in two consecutive posts.
Its compensation cap is determined by cc = gm1/(`M_TWO_PI*GBW*(1+1/a3)); The RHP zero and second pole are proportional to GBW. Why the phase margin decreases so much when GBW increases to 10GHz? Frz = GBW*pow(10,GainMargin/20); Wp2[0] = -`M_TWO_PI*Fpxo*Fpxo/Frz;
Quote:`include "discipline.h" `include "constants.h"
module OpAmp(out,inp,inm);
output out; input inp,inm; // single-ended output, differential input electrical out,inp,inm; voltage n0; // internal filter node (voltage only). electrical n1,n2; // midstage & output stage nodes.
// INSTANCE PARAMETERS: parameter real Vio=0; // input offset voltage (V) parameter real Rin=1e20; // opt. input resistance (ohms) parameter real Iib=0; // opt. input bias current (A) parameter real Ios=0; // opt. input offset current (A) parameter real Voh=5, Vol=0; // output high & low voltage limits (V) parameter real dVo=(Voh-Vol)/50; // output saturation corner rounding (V) parameter real Aol=74 from [0:120]; // DC gain (dB) parameter real Av=pow(10,Aol/20); // DC gain (V/V) [usu. computed from Aol] parameter real GBW=10M; // Gain-Bandwidth Product (Hz) parameter real Tr=0,Tf=0; // rise/fall times (to compute SRs) (sec) parameter real SRP=(Tr==0)?GBW:(Voh-Vol)/Tr; // positive slew rate (V/s) parameter real SRN=(Tf==0)?SRP:(Voh-Vol)/Tf; // negative slew rate (V/s) parameter real Tdhl=1/SRN; // delay leaving high saturation (sec) parameter real Tdlh=1/SRP; // delay leaving low saturation (sec) parameter real Fpxo=GBW*10 from [GBW*10m:GBW*1K]; // freq @ phase=-180deg (Hz) parameter real GainMargin=20 from [-30:60]; // gain margin (dB, >0 stable) parameter real CMRR=0; // opt. common mode rejection ratio (dB) parameter real Rdc=200; // output DC resistance (ohms) parameter real Rac=Rdc/4 from [Rdc*0.05:Rdc*0.8]; // output AC res (ohms) parameter real Isp=0, Isn=0; // opt. output source/sink current limits parameter integer Debug=0 from [0:3]; // [0=none, 1=params, 2=op.info, 3=iter] // LOCAL VARIABLES: real a3; // DC gain from midstage to output real Vin; // input voltage adjusted for CM term real Vhs; // half-scale output voltage swing range real gm1,ih1,il1; // transcond & current limits for source I1 real r1; // resistance R1 real vh2,vl2,dv2; // voltage limits & corner size for source E2 real cc; // coupling capacitance CC real gm3,vc3; // transcond and offset for source I3 real r3,ro; // resistances R3 & RO real ih4,il4; // currents @ voltage limits for source E4 real I1,I2,I3,I4,I5; // currents in five nonlinear dependent sources real Acm; // DC gain from CM input to differential input real Frz; // Frequency for RHP zero (hz) real Wp2[0:1]; // HF pole real & imaginary part (rad/s) // FUNCTIONS: ///// tanh transition between two levels: ftanh0(x,gain,ios,hi,lo) // Output ranges from lo to hi; out=0 occurs at x=ios, so // the function requires hi>0 and lo<0. analog function real ftanh0; input x,gain,ios,hi,lo; real x,gain,ios,hi,lo; real dv,argos; begin dv = (hi-lo)/2; // half of output range. argos = atanh(-lo/dv-1); // argument required to get out=0. ftanh0 = lo+dv*(1+tanh(gain*(x-ios)/dv+argos)); end endfunction
///// Voltage limiter: fivxlim(v,Vhi,Vlo,Ihi,Ilo,dV) // This is a smooth dual exponential relationship (dual diode limiter). // Specify dv much less than (Vhi-Vlo) for sharp limiting to occur. // The voltage vs current relation will pass through the following points: // Input Voltage: Vhi Vhi-dV (Vhi+Vlo)/2 Vlo+dV Vlo // Output Current: Ihi Ihi/100 0 -Ilo/100 -Ilo analog function real fivxlim; input v,Vhi,Vlo,Ihi,Ilo,dV; real v,Vhi,Vlo,Ihi,Ilo,dV; fivxlim = abs(Ihi)*exp(max(4.6*(v-Vhi)/dV,-30)) -abs(Ilo)*exp(max(4.6*(Vlo-v)/dV,-30)); endfunction |
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Best Regards, Yawei
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