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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Model Exponential rising signal in Verilog-A https://designers-guide.org/forum/YaBB.pl?num=1361159776 Message started by aliasnikhil on Feb 17th, 2013, 7:56pm |
Title: Model Exponential rising signal in Verilog-A Post by aliasnikhil on Feb 17th, 2013, 7:56pm Hi, I am trying to write VerilogA model for a circuit that has an exponentially rising output response (like charging of a real capacitor). For example, if the input is a voltage pulse with almost zero rise time, then the output of the circuit should rise exponentially towards the final voltage. I need this equation: V_out = V_previous + (V_new - V_previous)*(1 - exp(-1*time/tau)) V_previous is the starting voltage. V_new is the voltage that the output tries to reach exponentially. tau is the time constant. Can anyone please help me with this regard. Thanks. -Nikhil |
Title: Re: Model Exponential rising signal in Verilog-A Post by Geoffrey_Coram on Feb 21st, 2013, 10:15am You could implement an R and a C with Verilog-A equations. How are you thinking to "remember" the starting voltage? Code:
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