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Other CAD Tools >> Entry Tools >> Help! Synopsys dc_shell settings differences!
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Message started by Lightseed on Apr 2^nd, 2013, 2:52am

Title: Help! Synopsys dc_shell settings differences!
Post by Lightseed on Apr 2^nd, 2013, 2:52am

Can anyone please link or share the DEFAULT settings for synopsys dc_shell versions 2010.03-sp5 and 2011.09-sp5 ?

I am using them both to synthesize a digital verilog circuit, and in these 2 versions i get a totally different area for these 2 circuits. I can't find the default settings anywhere as they might influence the tool.