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General >> Tech Talk >> Why don’t analog to digital converters have integrated sampling clocks?
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Message started by Sharath Raju on Apr 9^th, 2013, 12:38am

Title: Why don’t analog to digital converters have integrated sampling clocks?
Post by Sharath Raju on Apr 9^th, 2013, 12:38am

I have often wondered why ADC manufacturers do not integrate the circuitry to generate the sampling clock within the ADC chip. From an end user perspective, it possibly saves the trouble of generating the sampling clock.

One reason I suspect is that the clock signal, which is a square wave, if decomposed into its fourier components can be composed of high frequency sinusoids that can “couple” into the circuit that handles the analog signal possibly causing a temporary change in the analog voltage level which in turn affects the level quantization.

Does anyone have a better way to explain the reason for not integrating the clock?

Thanks,
Sharath

Title: Re: Why don’t analog to digital converters have integrated sampling clocks?
Post by MikeL on Apr 10^th, 2013, 9:14am

I can think of two reasons (but there may be more).

Firstly, an external clock makes it easier to choose the sampling frequency. Not every application requires the maximum sample rate that you would have to provide with an internal clock. Sure, you could provide dividers or similar on the ADC chip but that makes the chip more complex.

Secondly, you have to share that clock with other digital elements of your application. Clock distribution is a science all of its own - but if you control the clock, you can include it within a phase locked loop (PLL) to cancel out delays in the distribution circuits.

Mike

Title: Re: Why don’t analog to digital converters have integrated sampling clocks?
Post by Sharath Raju on Apr 11^th, 2013, 9:37am

Thanks Mike.

I agree that a PLL can be used along with programmable dividers that allow different rates for the sampling clock.

I am not sure how my question relates to clock distribution, since, the clock signal is being distributed anyways. (My question is related to how to generate the clock source - by internal or external means).

Title: Re: Why don’t analog to digital converters have integrated sampling clocks?
Post by Sharath Raju on Apr 17^th, 2013, 11:42pm

Could someone please contribute to this thread?

Thanks in advance!

Title: Re: Why don’t analog to digital converters have integrated sampling clocks?
Post by raja.cedt on Apr 18^th, 2013, 2:57am

Hello Sharath,
how do you know that they are not integrating?? in fact They do. This depends on many things
1. When someone want to build complete system they have to integrate but people want to test first ADC without any further complications.

2. For example few ip companies sell only ADC ip, that means when you are going to buy and integrate with your system i am sure you will have some where one clock internal (if it is a high speed say few GHz) or very few external crystal clocks (around 100MHz which is typically called a system clock )

3. For a product people don't like integrate more than 1 PLL of course with some divider to satisfy all the blocks clocking requirements.

4. In fact forcing some external clock through a bond pad after 2GHZ is very difficult, even if you could manage to force through a strong driver still you will be limited by jitter, even on top of this this can coupled to supply though bond wire coupling.

5. Please refer the following pap in which they have integrated PLL.
a. A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS
b. A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB

6. Please have a look on attached fig and please note that this is my view, since i am not an ADC designer you are most welcome to correct if any thing wrong.

Thanks,
Raj.

Title: Re: Why don’t analog to digital converters have integrated sampling clocks?
Post by sheldon on Jun 3^rd, 2013, 12:27am

For what it is worth:

Why would you use power and area if the clock you needed was
already available? The answer probably also depends on what you
are designing. If you are integrating a low performance data
converter into an ASSP to reduce cost and a clock is available, then
you probably would use what you get. If your design requires
bleeding edge performance, you would probably spend more power,
area, and time on creating your own clock to reduce SNR loss due to
clock jitter.

Sheldon