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Other CAD Tools >> Entry Tools >> AMS elaboration errr in irun flow
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Message started by rajdeep on Apr 25^th, 2013, 9:21am

Title: AMS elaboration errr in irun flow
Post by rajdeep on Apr 25^th, 2013, 9:21am

Hi,

I am getting elaboration error when I try to run an AMS sim using irun flow of cadence.The error code is CUVPOM and its explanation is:
"The indicated port was either not declared in the instanced module, or it was mentioned too many times in the connection list".

The actual netlist is quite large so giving an example here.

Say, blockA is instantiated as follows in top module.
///////////////////////////////////////////////////////////////////
module TOP(in1,in2)
begin
output [1:0] in1;
output in2;
blockA u_blockA(.in1(in1), .in2(in2));
end

In the same cadence library block A is defined as:
module blockA(in1,in2);
begin
output [1:0] in1;
output in2;

endmodule
////////////////////////////////////////////////////////////////

No error is coming for in2, but for in1 which is a bus.

Can anyone please explain how to get rid of this. As I said the netlist is quite large and generated using VerilogIN of cadence from a synopsis generated netlist. No error or warning in verilogIn.

Thanks,
Rajdeep

Title: Re: AMS elaboration errr in irun flow
Post by rajdeep on Apr 25^th, 2013, 11:37pm

Hi All,

Just to close this thing, there was some port mismatch. Lesson learnt: whenever any such problem in Cadence AMS sims, try to open the concerned verilog files through the hierarchy editor! That tells exactly which designs it has picked up depending on the library definition. I was looking at wrong verilog files assuming the hierarchy editor was picking up them!

Best Regards,
Rajdeep