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Modeling >> Behavioral Models >> VerilogA Non Ideal OpAmp Model Voltage Limiting
https://designers-guide.org/forum/YaBB.pl?num=1372205785

Message started by aintk on Jun 25^th, 2013, 5:16pm

Title: VerilogA Non Ideal OpAmp Model Voltage Limiting
Post by aintk on Jun 25^th, 2013, 5:16pm

I am trying to build up a basic non-ideal opamp model in Verilog A and am having trouble understanding why my implementation of the voltage limiting doesn't function as I would expect it to(credit given to a model I saw somewhere that use an identical idea).

Specifically, when I run a DC sweep from -20 to 20(where vss=-15 and vdd=15), I observe ideal behavior. Any explanations/help would be very appreciated.

Code:

`include "constants.vams"
`include "disciplines.vams"

module ideal_opamp_va (vp, vn, vdd, vss, vout);
input vdd, vss, vn, vp;
output vout;
electrical vdd, vss, vn, vp, vout;

parameter real rin = 1M from (0:inf), //Input Resistance
g = 50000 from (0:inf), //Large Signal Voltage Gain
threedb=1M from (0:inf), //3dB Frequency
imax = 10m from (0:inf), //Maximum Ouput Current
ro = 50 from (0:inf); //Output Resistance

real vo_freq, io, vo, vomax, vomin;

analog begin
//definitions
vo = V(vout);
vomax = V(vdd);
vomin = V(vss);

//input current
I(vp,vn) <+ V(vp,vn)/rin + white_noise(4 * `P_K * $temperature/rin, "thermal") + flicker_noise(4 * `P_K * $temperature/rin, 1, "pink");

//frequency response
vo_freq = laplace_nd(V(vp,vn)*g, {1}, {1, 1/(`M_TWO_PI*threedb)});

//output current
io = (vo_freq-V(vout))/ro;

// limit output voltage
if (V(vout) >= 0)
io = io*tanh((vomax-V(vout)));
else
io = io*tanh(abs(vomin-V(vout)));

//output current limit
if (I(vout) > imax)
io = imax;

if (I(vout) < -imax)
io = -imax;

I(vout) <+ slew(io,threedb*imax);

end
endmodule

Title: Re: VerilogA Non Ideal OpAmp Model Voltage Limiting
Post by boe on Jun 26^th, 2013, 1:16am

aintk wrote on Jun 25^th, 2013, 5:16pm:

... my implementation of the voltage limiting doesn't function as I would expect it to...
Specifically, when I run a DC sweep from -20 to 20(where vss=-15 and vdd=15), I observe ideal behavior.

So, what does it (not) do?

The code works by limiting the output current near vout_max/min.

- B O E

Title: Re: VerilogA Non Ideal OpAmp Model Voltage Limiting
Post by aintk on Jun 26^th, 2013, 2:24pm

I first ran a simulation that did a dc sweep between -20 and 20V while the amplifier was in unity gain feedback. The output still saw a normal -20 to 20V ramp without the clipping I would expect.

I figured there might be an issue with starting in an invalid range so i also did a test for 0 to 20V where I saw the same behavior(no clipping at 15V just a ramp).

Thanks for the help.

Title: Re: VerilogA Non Ideal OpAmp Model Voltage Limiting
Post by boe on Jun 27^th, 2013, 3:23am

aintk,
oh, ideal = not clipping.

- B O E

Title: Re: VerilogA Non Ideal OpAmp Model Voltage Limiting
Post by weber8722 on Mar 1^st, 2015, 11:04am

Hi,

best test the model 1st without feedback, this makes life much easier!
Instead of the horrible 2 if-statements better use the min and max functions (or make little macros).

ylimited=max(ymin,min(y,ymax)); // :)

Bye Stephan