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Modeling >> Behavioral Models >> DPSK modulator
https://designers-guide.org/forum/YaBB.pl?num=1372336495

Message started by sarge on Jun 27^th, 2013, 5:34am

Title: DPSK modulator
Post by sarge on Jun 27^th, 2013, 5:34am

Hi

I try to build DPSK binary modulator with using VerilogA.

Here my code:

Code:

`include "constants.vams"
`include "disciplines.vams"

module DPSKModulator(in, clk, out);
input in;
input clk;
output out;

electrical in;
electrical clk;
electrical out;

parameter real Amplitude = 0.2;
parameter real Freq = 4G;
parameter real vth = 0.6; //Threshold voltage
parameter real offset = 0;
real phase;
real Krand;
real Krandlast;

analog begin

@(initial_step) phase = 0;

@(cross(V(clk) - vth, +1))
begin //On rising edge clk
if (V(in)>vth)
phase = phase + `M_PI;

end

V(out) <+ Amplitude*sin(2*`M_PI*Freq*$abstime + phase)+offset;

end

endmodule

Clock frequency is double data frequency.

It is works, but there are peaks on carrier frequency on spectrum:

In same time, i built bpsk modulator in manner like above and it is works fine.

In what could be the problem? How I can remove these peaks?

Title: Re: DPSK modulator
Post by Ken Kundert on Jun 27^th, 2013, 8:48am

In general you would have been better served if you also showed the time domain waveforms so we could look for unusual artifacts. However, you made two classic mistakes, and you will probably get better results if you fix those.
1. You are generating a sinusoid at a frequency that is much higher than any input frequency and yet you have no $bound_step function to prevent aliasing/Nyquist problems.
2. You are abruptly changing the phase and yet you have no transition function to control the transition times.
In addition, your initialization of phase to 0 is unnecessary, it defaults to 0.

You might try something like this:

Code:

module DPSKModulator(in, clk, out);
input in; electrical in;
input in; electrical clk;
output out; electrical out;
parameter real Amplitude = 0.2;
parameter real Freq = 4G;
parameter real vth = 0.6; //Threshold voltage
parameter real offset = 0;
real phase;

analog begin
@(cross(V(clk) - vth, +1)) begin
if (V(in) > vth)
phase = phase + `M_PI;
end
V(out) <+ Amplitude*sin(2*`M_PI*Freq*$abstime + transition(phase, 0, 1n))+offset;
$bound_step(0.1/Freq);
end
endmodule

-Ken

Title: Re: DPSK modulator
Post by sarge on Jun 28^th, 2013, 6:42am

Thanks for responce!

I tried to build it as you advised (but i changed transition time to 50ps, 1ns very big for 4GHz signal) and i got same pictures as above.

Here piece of transient waveforms: