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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Spice from Verilog using V2LVS command in Calibre (need to simulate)
https://designers-guide.org/forum/YaBB.pl?num=1374684842

Message started by ic_engr on Jul 24^th, 2013, 9:54am

Title: Spice from Verilog using V2LVS command in Calibre (need to simulate)
Post by ic_engr on Jul 24^th, 2013, 9:54am

Hello

I have a diigital GDS. I used 'v2lvs' command in Calibre to get the spice generated to perform LVS. All went okay.

I now want to perform simulation in Cadence in spectre. To do this,
I converted the spice file using 'spp -convert ...
and got the spectre file .scs.

When I simulated now, its complaining about "Unexpected equals "="/ Expected end of line".. this is happpening since the file has port assignments like a=adc_bit<0>. it seems it wants me to put the net into double quotes.

Any suggestions why ?

ic_engr