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Design >> High-Speed I/O Design >> Self bias PLL
https://designers-guide.org/forum/YaBB.pl?num=1376936867

Message started by raja.cedt on Aug 19^th, 2013, 11:27am

Title: Self bias PLL
Post by raja.cedt on Aug 19^th, 2013, 11:27am

Hello,
Can any one please explain what is the the dis-advantage of self bias PLL (PVT robust), i haven't seen any one using self bias PLL now a days. Mostly i have seen supply regulated self bias many papers from Rambus, true circuits using this long back, but don't know why there are not using now.

Thanks,
Raj.

Title: Re: Self bias PLL
Post by carlgrace on Feb 23^rd, 2014, 9:10pm

This is an old post but maybe someone is still interested...

The biggest problem with the self-biased PLL is that the oscillator isn't as fast as possible in a given technology. Nowadays people want to go as fast as possible. I use the self-bias PLL exclusively in my designs. I understand it and it works.

I think it has only disappeared from the leading-edge research zone PLLs. I suspect it is quite well-used in practice still.