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Design >> Mixed-Signal Design >> Discrete time delta-sigma ADC
https://designers-guide.org/forum/YaBB.pl?num=1377836008

Message started by Chuck on Aug 29^th, 2013, 9:13pm

Title: Discrete time delta-sigma ADC
Post by Chuck on Aug 29^th, 2013, 9:13pm

Hey guys,

I was reading a tutorial published by TI, and it was about continuous time delta sigma (DS) ADCs. Author wanted to compare discrete versus continuous time DS ADCs, and he said "in discrete time delta sigma ADC , unlike continuous time, the internal amplifiers must settle within some target resolution each period."
No doubt that continuous time delta sigma has higher speed but lower resolution compared to discrete time, but I am not still clear about the part he claimed "amplifiers must settle within some target resolution". They should settle, but is there any target resolution for settling?
I thought as long as they settle, it doesn't matter since it won't introduce any non linear error.
Aside from that, since delta sigma ADCs are high resolution converters, say more than 18 bits, does it mean in each period amplifier should settle within this range: Vref/2^N ? where Vref is reference voltage of the ADC, and N is the resolution of the entire converter.

Title: Re: Discrete time delta-sigma ADC
Post by eternity on Sep 20^th, 2013, 7:40am

Can you kindly share more info on the source of tutorial you were talking about? It would make things easier for us to discuss about this query

For your query if I understand it right,

In my opinion, irrespective of the resolution of the converter, the slew rate specifications for the loop filter should be satisfied by the designer. Please keep in mind under-rating the slew rate property might introduce considerable non-linearity to the already complex DS architecture. This specific complexity increases directly proportional with the increase in the number of bits for the quantiser.

for your query on'does it mean in each period amplifier should settle within this range: Vref/2^N ? where Vref is reference voltage of the ADC, and N is the resolution of the entire converter.', I would expect it to be more clear for others to understand and answer it

Title: Re: Discrete time delta-sigma ADC
Post by weber8722 on Feb 27^th, 2015, 10:45am

Hi,

this is one potential advantage of CT vs DT, but of course they are others as well :

- less impact of flicker noise
- usually works with smaller caps
- has some intrinsic antialising filter
- less kickback to ADC input
- typically better at high input frequencies (like >30MHz)

but also some disadvatages:

- DAC should use RZ coding
- big RC tolerances may require some kind of calibration

The higher slewrate/speed for DT may also be adressed with other means, like input feedforward (of course also possible in CT).

But there is no free lunch....

Bye Stephan