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https://designers-guide.org/forum/YaBB.pl Analog Verification >> Analog Functional Verification >> Understanding resistor usage https://designers-guide.org/forum/YaBB.pl?num=1378840868 Message started by GregS on Sep 10th, 2013, 12:21pm |
Title: Understanding resistor usage Post by GregS on Sep 10th, 2013, 12:21pm Friends, I'm new to Verilog-A/Verilog-AMS, and I've run into something that I can quite explain. I've tried to setup a resistive load on an electrical input to my model, and I get an error from the simulator when I use one coding style over another. The message looks like this: FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit I thought this code was equivalent, but obviously it's not, or I have an error somewhere else. Coding example #1: Define a resistor model like this: module res (PLUS, MINUS ); inout PLUS, MINUS; electrical PLUS, MINUS; parameter real r=1 exclude 0; analog begin I(PLUS,MINUS) <+ V(PLUS,MINUS)/r; end endmodule Instantiate this reistor model in another model like this: module blah (VDDIO, VSS); inout VDDIO; inout VSS; electrical VDDIO; electrical VSS; real Ivddio; res #(.r(10k)) load7 (.PLUS(VDDIO), .MINUS(VSS)); analog begin Ivddio = I(VDDIO,VSS); <--This creates an error during simulation end endmodule Coding example #2: module blah (VDDIO, VSS); inout VDDIO; inout VSS; electrical VDDIO; electrical VSS; real Ivddio; analog begin I(VDDIO,VSS) <+ V(VDDIO,VSS)/10k; Ivddio = I(VDDIO,VSS); end endmodule In the 2nd example, I'm not instantiating the resistor, I'm simply encoding the resistive load into the voltage to current relationship, and 2nd example operates like I expect, no errors and I can monitor my current through the resistive load in simulation In the first example, if I code the line to monitor the current, the FATAL error occurs. Any ideas why this is treated differently? I must be missing something basic. Thanks for your help..... |
Title: Re: Understanding resistor usage Post by boe on Sep 12th, 2013, 4:32am GregS, The error shows you have shorted two (ideal) voltage sources (the other is probably in the testbench). Because there is no branch between the nodes in ex. 1, the simulator has to add a source to measure the current (NB: an ideal amp meter is a short). In ex. 1, you should measure the current through a port or from blah.VDDIO to blah.res.PLUS. - B O E |
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