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Design Languages >> Verilog-AMS >> Encrypting verilog-A model in HSPICE
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Message started by yueguoguo on Sep 17^th, 2013, 9:41pm

Title: Encrypting verilog-A model in HSPICE
Post by yueguoguo on Sep 17^th, 2013, 9:41pm

Does anyone have an idea about whether HSPICE can be used to encrypt/decrypt a Verilog-A model file.

Thanks.

Title: Re: Encrypting verilog-A model in HSPICE
Post by Geoffrey_Coram on Nov 5^th, 2013, 8:26am

There is no encryption in the Verilog-A standard. It might be possible to compile the Verilog-A into a shared object file and distribute that binary file instead of the source code, which isn't really encryption.