The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Analog Verification >> Analog Performance Verification >> Design for Testability for non-logic circuits
https://designers-guide.org/forum/YaBB.pl?num=1379836424

Message started by @@k@sh on Sep 22^nd, 2013, 12:53am

Title: Design for Testability for non-logic circuits
Post by @@k@sh on Sep 22^nd, 2013, 12:53am

Hi everyone,
DFT enables to identify the exact failure location in logic circuit. Just want to know if there exist similar concept for Analog/RF circuits.
If chip doesn't work on fabrication, how does one debug which block of it not working? May be one can have pads for direct-probing at i/p & o/p of each block. But then need to isolate the preceding & following stages. What are the built-in self testing techniques for Analog/RF.
Comments welcomed....Resources for detail reading appreciated