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Analog Verification >> Analog Functional Verification >> Module access to instance name
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Message started by InTheMiddle on Oct 2^nd, 2013, 3:30pm

Title: Module access to instance name
Post by InTheMiddle on Oct 2^nd, 2013, 3:30pm

Is there a way for the module to access it's instance name and display in the standard output?

Thanks in advance.

Regards,

InTheMiddle

Title: Re: Module access to instance name
Post by Andrew Beckett on Dec 27^th, 2013, 1:38pm

In Verilog (or Verilog-AMS) you can use: $strobe("My name is %M"); to do this.

Regards,

Andrew.