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Simulators >> Circuit Simulators >> Convergence Issue in Monte Carlo Simulations
https://designers-guide.org/forum/YaBB.pl?num=1383462358

Message started by jockeymonto on Nov 3^rd, 2013, 12:05am

Title: Convergence Issue in Monte Carlo Simulations
Post by jockeymonto on Nov 3^rd, 2013, 12:05am

Hi,

I have a simple two diode connected npn bjt circuit where both the npns are biased thru their emitters. But when i run MC transient simulations for the difference in theri emitter base voltages I get convergence errors. Out of 200 runs only 3 are simulated. The problem is likely to be with the 'Transients Options' form. When I press 'skipdc' option to yes I get no convergence issues but a lot of transients at the DC. When I press 'skipdc' to no I get convergence issues. I have tried many things on the transient options form like 'Integration Methods Parameters', Iteratio' option, 'cmin' etc but to no avail. I need solution to this convergence issue.The image attached shows the transient simulation options I am using.

Output log file says to loosen tolerance like 'iabstol' on options paramter, but I can't find it anywhere. I also said couple of other things which I tried but nothing happened.

I am not getting any convergence error for a single run normal Transient simulation but only for Monte Carlo.

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by sheldon on Nov 8^th, 2013, 5:47am

Jockey,

From the available information it is a little difficult to guess what the
issue is. Since non Monte Carlo simulation runs properly, the first
question is how is the Monte Carlo model implemented. Next, why
are you using transient analysis to measure the difference in
base-emitter voltage? Isn't a dc sweep sufficient? Since it would
eliminate the issues with transient setup. Finally, iabstol is a simulator
option not an analysis options, simulation --> options.

Sheldon

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by jockeymonto on Nov 8^th, 2013, 11:27am

Hi Sheldon,

I have pasted a detailed reply to the same issue in Cadence forum at the following link:

http://www.cadence.com/Community/forums/p/27687/1328494.aspx#1328494

Have a look at this.

Plus my problem is I am getting weird transients at DC and it takes some time before the output is finally settled. So with DC sweep I can't and am not getting the right results.

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by sheldon on Nov 9^th, 2013, 4:12am

Jockey,

First you are using pnp transistors not npn transistors. Next,
a few questions:
1) Why do it this way?
Why not two current sources of the same value and size
one of the pnp transistors?

2) Next you are operating these transistors at very low
current density, have you checked the p-channels models
subthreshold characteristics?

3) Again, why are you performing transient analysis on this
circuit? You are just looking at the temperature tracking,
then dc analysis is all you need. For example, when
performing a similar analysis of a bandgap reference, only
need to run dc in order to verify trimming ranges.

4) What other parameters are you tracking in your analysis? For
example, how much head room do the current source have?
Is there any reason that the circuit is might be having issues
setting up? Looking at your schemtic, it does not seem like
there should be any issue, but it might be worth checking.

Sheldon

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by rfidea on Nov 9^th, 2013, 5:21am

I looked at your schematic and there is no bulk connection to the vpnp:s, as far as I can see. I do not know how your PDK works but somewhere there must be a connection to deep-nwell region around and under the the vpnp.

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by sheldon on Nov 9^th, 2013, 5:32am

The question is, are the vertical pnp built with substrate as the collector.
If the vertical pnp transistors are substrate pnp transistors, then a
fourth terminal is not required since by definition the third terminal,
collector, and fourth terminal, substrate, are connected. Using
substrate pnp transistors for diodes is not an issue.

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by rfidea on Nov 9^th, 2013, 7:11am

Sheldon, you are right. I'm very used to BiCMOS design where the high performance vpnp is placed in an isolated well. I suppose this issue is in a pure cmos technology since there is no fourth terminal at the device.

Title: Re: Convergence Issue in Monte Carlo Simulations
Post by jockeymonto on Nov 9^th, 2013, 7:51am

Dear sheldon adn rfidea,

Yes I am using GF 65nm technology with substrate vpnp, so the substrate serves as collector terminal.

I am not using vpnps with different area and same current density because the error introduced due to process spread will be many times more.

I have to keep the current density low to minimize the impact of emitter base series resistance which further introduces error.

Any way I am looking into suggestions and will keep updated.