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Design Languages >> Verilog-AMS >> constrain number of bits
https://designers-guide.org/forum/YaBB.pl?num=1384410936

Message started by aaron_do on Nov 13^th, 2013, 10:35pm

Title: constrain number of bits
Post by aaron_do on Nov 13^th, 2013, 10:35pm

Hi all,

first off I am new to Veriloga. I am trying to model a digital control loop, but I am storing variables as "real" type. I would like to constrain the resolution of my signals to a certain number of bits to make the system more realistic. Is there any way to do this?

I'm thinking I need the simplest possible ADC function. What I've come up with is :

var = var - var % resolution;

where var is the number I want to constrain, and % is the modulus function. Not sure if this works or if there's a better way though.

thanks,
Aaron

Title: Re: constrain number of bits
Post by boe on Nov 14^th, 2013, 6:26am

Hi Aaron,
your idea is equivalent to rounding towards zero in steps of resolution (sign of % is sign of first operand).
Alternatives are
Code:

resolution * ceil(var / resolution)

or
Code:

resolution * floor(var / resolution)

(rounding towards +/-infinity).
- B O E

Title: Re: constrain number of bits
Post by aaron_do on Nov 14^th, 2013, 8:55pm

Thanks!