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Design Languages >> Verilog-AMS >> Passing CDF parameters in a text based testbench
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Message started by Amblik on Dec 12^th, 2013, 11:26am

Title: Passing CDF parameters in a text based testbench
Post by Amblik on Dec 12^th, 2013, 11:26am

Hi Folks, first post though i've been lurking this site for ages.

I'm starting to get to grips with verilog-ams test benches (purely text)

I was wondering how to go about passing parameter right through from ADE (Cadence) to model?

If i used a schematic testbench i can simply set variables for the CDF values in the form when i "Q" on the DUT.

How do i get the ADE to recognise parameters in a text based test bench?

Thanks.

Title: Re: Passing CDF parameters in a text based testbench
Post by boe on Dec 13^th, 2013, 10:07am

Amblik,
Did you look at the V-AMS netlist of a schematic using such parameters?
- B O E

Title: Re: Passing CDF parameters in a text based testbench
Post by Amblik on Dec 13^th, 2013, 10:58am

I didn't even think of that!

I see my variables appearing in the netlist as such:

Code:

module cds_globals;
...
// Design Variables
dynamicparam real variable1 = 100m;
dynamicparam real variable2 = 200m;
endmodule

So am i correct in assuming that if i instantiate a module such as that above in my top level (text based) testbench, i'll be able to see my variables in ADE?

Thanks B O E.

Title: Re: Passing CDF parameters in a text based testbench
Post by boe on Dec 17^th, 2013, 8:21am

Amblik,
the cds_globals cell is (for schematic-on-top) created by ADE (from the design parameters you have listed there) and automatically included in the netlist.
Actually, I have not yet done V-AMS-on-top with ADE: so far, we have always used a script/make flow for text-on-top, writing our own code for cds_globals. Thus, I cannot give you a definite answer how to do this...
- B O E

Title: Re: Passing CDF parameters in a text based testbench
Post by Andrew Beckett on Dec 27^th, 2013, 10:56am

If you create a module with parameters (using the Verilog-AMS parameter statement), then when Virtuoso parses that module, it will create CDF parameters from these Verilog-AMS parameters. Consequently, when you instantiate the block, you will see those parameters on the create instance or edit properties form.

If you use global (design) variables, these will get netlisted as parameters in the cds_globals module and then are referenced using an out-of-module reference.

So it's pretty straightforward, really... (unless I've misunderstood what you're asking).

Regards,

Andrew.

Title: Re: Passing CDF parameters in a text based testbench
Post by Amblik on Feb 24^th, 2014, 8:07am

Andrew Beckett wrote on Dec 27^th, 2013, 10:56am:

Hi Andrew, thanks very much for your reply. Apologies for the long delay, i thought i would get an email notification when this thread was replied to.

I'm actually still having this problem. I understand that if my module has parameters, i can change those parameters in the create instance/edit properties forms. Then if i set those parameters to variables i can copy variables from cell view into my ADE.

However, if i'm not mistaken, this is if i have a schematic flow where i can see the module instantiated and consequently click on it to edit the properties. I don't have any schematics in my flow and it is purely text. As such, when i instantiate my modules in the test bench, how do i pass variables from the ADE to the testbench/module/DUT?

Thanks and regards.

Title: Re: Passing CDF parameters in a text based testbench
Post by Andrew Beckett on Feb 24^th, 2014, 11:39am

Design Variables in ADE end up in the cds_globals module, and hence can be referred to using an Out-Of-Module-Reference.

For example:

Code:

vsource #(.type("pulse"), .val0(0), .val1(2.5),
.period(1/cds_globals.fREF), .delay(0), .rise(100p), .fall(100p),
.width((0.5/cds_globals.fREF)-100p), .fundname("nameREF")) V6 (
CLK_REF, cds_globals.\gnd! );

In this case, I had an ADE variable called fREF - and you can see that I'm passing it to an instance of vsource (in this case that's a built-in primitive, but it could equally well be an instance of a VerilogAMS module).

So you'd just need to use similar coding in your textual representation of the design. For example, here's what I get in the auto-generated cds_globals module in my case:

Code:

module cds_globals;

// Global Signals
wire \VDD! ;
wire \VSS! ;
electrical \gnd! ;
ground \gnd! ;

// Design Variables
dynamicparam real fREF = 25M;
dynamicparam real anotherVar = 2.5;

endmodule

Two variables, fREF and anotherVar.

Regards,

Andrew.

Title: Re: Passing CDF parameters in a text based testbench
Post by Amblik on Feb 24^th, 2014, 11:47am

This is great! So simple! Thanks very much. That's solved a lot of problems for me. I hadn't even thought of referring to cds_globals as a module.

Thanks again!