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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Supply Sensitivity in a Verilog-AMS testbench https://designers-guide.org/forum/YaBB.pl?num=1387738613 Message started by Amblik on Dec 22nd, 2013, 10:56am |
Title: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Dec 22nd, 2013, 10:56am Hi Everyone, i'm having trouble at the moment as i am verifying a top level which has multiple supplies. I'm using supply sensitive connect modules and my functional models all have supply sensitive statements in there IO list. My top level testbench is text based VerilogAMS. My problem is when it comes to doing mixed level simulations. When i swap one of my instantiated models for the schematic equivalent, i have errors with the supply sensitive connect modules. All the 'solutions' i've found involve changes parameters of the pins or of the block itself by clicking on visual items etc on the schematic. Obviously i can't do that in a text based testench. I've blindly tried adding the same supply sensitive statements in my testbench but since there are no inputs/outputs in the testbench, it doesn't work. Does anyone have any ideas or can they point me in the direction of where i could find the info? Thanks in Advance. |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Andrew Beckett on Dec 27th, 2013, 10:42am You probably need to provide a bit more info on precisely what you're doing and what the error messages you're getting are - it's a bit hard to know what's wrong when you've not supplied much information, unfortunately. Kind Regards, Andrew. |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Jan 21st, 2014, 2:18am Hi Andrew, thanks for the reply. Apologies for the delay, i didn't realise you had replied to this topic ( i thought i would get an email notification!) I'm still having no luck with this situation. I've created a testcase library which i forwarded to our EDA/CAD guys but i still haven't had any resolution. I apologise in advance for the size of this post but i will try and detail the scenario as much as possible. I have a top level testbench called tb_supply_sensitive_testcase which has the following views: verilogams - the verilogams text based tesbench (shown below) schematic - the schematic equivalent of the vams testbench config_sch - the config view where everything is in schematic config_vamstb_schdut - config where tb is vams, instantiated blocks are schematic config_vamstb_vamsdut - config where everything is vams ams_state_config_sch - simulation state for config_sch ams_state_vamstb_schdut - simulation state for vamstb/sch blocks ams_state_vamstb_vamsdut - state for everything in vams I then have 4 cells: logic_cell_1_5v - an AND gate from a 7v library logic_cell_2_1v8 - an AND gate from a 1.8v library LS_down_5v_to_1v8 - a "Down" Levelshifter (a 7v buffer) LS_up_1v8_to_5v - an "Up" Levelshifter All of which have 3 views: symbol schematic verilogams Where the verilogams view is a direct representation of the schematic but they include supply sensitivity statements on the IOs. The verilogams testbench is as follows: Code:
And the following code is the verilogams views of the 4 cells instantiated in the testbench. Code:
Code:
Code:
Code:
Obviously i can't give the schematics but as i said above they are direct representations of the verilogams views. Oops run out of characters, i'll follow up in a second post. Thanks. |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by boe on Jan 21st, 2014, 2:27am Hi Amblik, From a first look on your models: I recommend to explicitly define all digital interface nets of your models as discipline logic. Also: did you use discipline resolution mode detailed? - B O E [edit]And you should not use supply attributes on VSS.[/edit] |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Jan 21st, 2014, 3:53am So to continue on from the previous post... I have a testbench with 2 power supplies; 5v and 1.8v. I also have 4 instantiated cells which use the 2 power supplies. I'm trying to simulate with supply sensitive connect modules with Virtuoso ADE L, simulator set to AMS, and the netlister set to use the OSS based netlister with irun. I now have 2 scenarios: 1. Everything in verilogams - Everything works, the supply sensitivity statements in the models take care of the connect modules and we are all ok! 2. Trying to set any or all of the instantiated blocks to schematic. I get error messages that the supply sensitivity is not set for pins on the blocks etc. Error messages similar to: Code:
The above error message is from the ams_state_vamstb_schdut. I know that i need to set supply sensitivity for the instantiated blocks. However, i'm not sure how. Any help would be greatly appreciated! Thank you. |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Jan 21st, 2014, 4:01am boe wrote on Jan 21st, 2014, 2:27am:
Thanks for your reply, i am using detailed discipline resolution. Sorry, i've just noticed that i had supply sensitivity set for VSS, this is a mistake. Good catch! I didn't mean to do that and i only ever set supply attributes for digital pins. In the future i'll declare my digital interfaces as logic discipline. Is this a matter of good style? I'm always interested in better coding practices! Thanks again |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by boe on Jan 21st, 2014, 4:25am Amblik wrote on Jan 21st, 2014, 4:01am:
Code:
Oh, and did that help? - B O E |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by boe on Jan 21st, 2014, 4:36am Amblik wrote on Jan 21st, 2014, 3:53am:
It looks as if you try to stimulate a schematic w/ digital input. Then you need a CM at the input of the schematic to convert the signal to electrical. This will obviously need sensitivity attributes.... You can either change the stimulus to analog or add properties to the schematic ports. I do not understand why you should get Code:
- B O E |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Jan 21st, 2014, 4:44am boe wrote on Jan 21st, 2014, 4:36am:
Adding properties to the schematic ports is essentially what i'm trying to do. However, i'm not sure how to achieve that. Any thoughts? Thanks. |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by boe on Jan 21st, 2014, 4:58am Amblik wrote on Jan 21st, 2014, 4:44am:
In (recent versions of) Cadence Schematic/Symbol editor, the "object property" form offers "pwr/gnd sensitivity" for pins. - B O E |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Jan 21st, 2014, 5:42am boe wrote on Jan 21st, 2014, 4:58am:
Well now!! This appears to work! There is a "but" though. (And it's quite a big but!). It's quite labor intensive! There's no way i'd be able to go through every pin in a top level IC and set the attributes. Is there a quicker way to do this? We're so close! Also, when i edit the pin properties for schematic/symbol and then check and save, i get warnings that the pins don't match the verilogams view? Do you have an idea of why it might be saying that? How to get rid of the warnings? Thank you very much! |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by boe on Jan 21st, 2014, 6:05am Amblik wrote on Jan 21st, 2014, 5:42am:
Or you can write a stimulus generator (w/ supply attrib's) and place it in your TB. If the attrib's match, it should work w/o warnings (haven't used it for a while, though). - B O E |
Title: Re: Supply Sensitivity in a Verilog-AMS testbench Post by Amblik on Jan 21st, 2014, 6:16am boe wrote on Jan 21st, 2014, 6:05am:
To be honest, the more i think about it, i might have to make it stimulus based to get round this. I didn't really want to do that. (although i'm not really sure WHY i didnt really want to do that! If it makes any sense! Thanks again for your help! |
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